tag:blogger.com,1999:blog-71697685015638081072024-02-19T08:42:20.815-08:00Quad-Core-CPUQuad-core from Intel& AMDUnknownnoreply@blogger.comBlogger14125tag:blogger.com,1999:blog-7169768501563808107.post-39009077646626223522015-08-02T09:23:00.001-07:002015-08-02T09:23:00.766-07:00Windows 10's usage share jumps 4x in three days<div id="article_topic" style="margin: 0px; padding: 8px 10px; border-width: 0px 0px 3px; border-style: none none solid; border-bottom-color: rgb(235, 235, 235); outline: none 0px; font-weight: bold; vertical-align: baseline; -webkit-box-shadow: rgb(204, 204, 204) 0px 20px 20px -20px inset; box-shadow: rgb(204, 204, 204) 0px 20px 20px -20px inset; clear: both;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">WINDOWS </span></div><h1 style="margin: 0px; padding: 10px 10px 0px; border: 0px none; outline: none 0px; font-weight: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><a href="http://m.itnews.com/windows/95330/windows-10s-usage-share-jumps-4x-three-days" title="Windows 10's usage share jumps 4x in three days" class="active" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-weight: bold; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; text-decoration: none; background-position: 0px 0px; background-repeat: repeat repeat; font-size: 17px; -webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);"><font color="#000000">Windows 10's usage share jumps 4x in three days</font></a></h1><div id="date" style="margin: 0px; padding: 7px 0px 7px 10px; border: 0px none; outline: none 0px; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Aug 02, 2015 08:07 am | <a href="http://www.computerworld.com/" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; text-decoration: none; word-wrap: break-word; background-position: 0px 0px; background-repeat: repeat repeat;">Computerworld </a></span></div><div id="deck" style="margin: 0px; padding: 0px 0px 0px 10px; border: 0px none; outline: none 0px; font-weight: bold; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Microsoft's Windows 10 got off to a roaring start in its first few days.<br><br><i style="background-image: none; background-attachment: scroll; border: 0px none; margin: 0px; outline: none 0px; padding: 0px; font-weight: normal; background-position: 0px 0px; background-repeat: repeat repeat;">by Gregg Keizer</i></span><div id="twitter" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-weight: inherit; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"></div><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);"><br></span><div class="actions_fb" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-weight: inherit; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><div style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-weight: inherit; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"></div></div></div><div class="green_hr" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"></div><div id="articleContent" style="margin: 10px 0px 0px; padding: 0px 0px 10px; border-width: 1px 0px 0px; border-style: solid none none; border-top-color: rgb(204, 204, 102); outline: none 0px; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Microsoft's Windows 10 got off to a roaring start in its first few days, with its initial usage share handily trumping that of the firm's last free upgrade, Windows 8.1, data from a Web analytics vendor showed.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Worldwide, Windows 10's usage share -- a measure of how active users of the OS were on the Internet, not the number of users or PCs running the operating system -- doubled from 0.3% to 0.6% on the official launch day of July 29, according to Irish metrics company StatCounter.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">By the end of Saturday, Aug. 1, Windows 10's global usage share had climbed to 2.5%.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">In the United States, the surge of Windows 10 -- which was offered as a free upgrade to most consumers and small businesses running either Windows 7 or Windows 8.1 -- was even more impressive. By Saturday, the U.S.-only usage share of Windows 10 stood at 3.7%.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Windows 10's usage share jump, both worldwide and in the U.S., was dramatically larger than the increase posted by Windows 8.1 in mid-October 2013, when Microsoft offered the revised OS as a free upgrade to those then running Windows 8.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Windows 8.1's usage share topped out at 0.6% -- both globally and in the U.S. -- on the third day after its debut, a fourth (worldwide) and a sixth (U.S.) of Windows 10.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">The larger increases were expected: Windows 10's pool of potential upgraders was massive compared to Windows 8.1's, because Windows 7, the dominant operating system both worldwide and in the U.S., was included. And the fact that Windows 10 is, unlike 8.1, a major upgrade -- the latter was a minor refresh -- with a restored Start menu, integrated Cortana and loads of other new features, plays in 10's favor.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Microsoft has also aggressively promoted Windows 10 and the free upgrade with an unprecedented effort that dwarfed any to get users to adopt Windows 8.1 two years ago. This spring, for instance, the Redmond, Wash. company added an app to hundreds of millions of Windows 7 and 8.1 devices that trumpeted the free upgrade, put a one-year time limit on the deal to accelerate adoption and recently began a multimillion-dollar advertising campaign.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">Microsoft has only said that <a href="http://www.computerworld.com/article/2955282/operating-systems/microsoft-scores-with-free-windows-10-upgrade-as-downloads-tally-10x-windows-8s-first-day-sales.html" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; text-decoration: none; word-wrap: break-word; background-position: 0px 0px; background-repeat: repeat repeat;">there are were 14 million devices running Windows 10</a> within the first day of issuing the final code, a number that presumably included the approximately 5 million it previously said were using the OS's preview provided to members of its Insider program.</span></p><p style="margin: 15px 10px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; word-wrap: break-word; background-position: 0px 0px;"><span style="-webkit-text-size-adjust: auto; background-color: rgba(255, 255, 255, 0);">StatCounter measures page views to the sites that deploy its analytics, signaling how actively users of a specific operating system browse the Web.</span></p><div><br></div></div><div id="block-block-14" class="block block-block region-odd odd region-count-1 count-1" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-size: 16px; font-family: Arial, Helvetica, sans; vertical-align: baseline; background-image: none; background-attachment: scroll; -webkit-text-size-adjust: auto; background-position: 0px 0px; background-repeat: repeat repeat;"><div class="content" style="margin: 0px; padding: 0px 10px; border: 0px none; outline: none 0px; font-style: inherit; font-family: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><div id="recommended_links" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; font-family: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><div class="OUTBRAIN" data-src="http://itnews.com/node/" data-widget-id="AR_1" data-ob-template="itnews" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; font-family: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"></div></div></div></div><div id="block-block-13" class="block block-block region-even even region-count-2 count-2" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-size: 16px; font-family: Arial, Helvetica, sans; vertical-align: baseline; background-image: none; background-attachment: scroll; -webkit-text-size-adjust: auto; background-position: 0px 0px; background-repeat: repeat repeat;"><div class="content" style="margin: 0px; padding: 0px 10px; border: 0px none; outline: none 0px; font-style: inherit; font-family: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"><div id="whitepaper_btm" style="margin: 0px; padding: 0px; border: 0px none; outline: none 0px; font-style: inherit; font-family: inherit; vertical-align: baseline; background-image: none; background-attachment: scroll; background-position: 0px 0px; background-repeat: repeat repeat;"></div></div></div>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-36939513457856381852012-07-07T12:59:00.002-07:002012-07-07T13:02:52.097-07:00Desktop 3rd Generation Intel® June 2012 Specification Update<br />
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<br />
<br />
Reference Number: 326766-004<br />
Desktop 3rd Generation Intel®<br />
Core™ Processor Family<br />
Specification Update<br />
June 2012 Specification Update<br />
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY<br />
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN<br />
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS<br />
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES<br />
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER<br />
INTELLECTUAL PROPERTY RIGHT.<br />
A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. <br />
SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND<br />
HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF<br />
EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF,<br />
DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH<br />
MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN,<br />
MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.<br />
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or<br />
characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no<br />
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without<br />
notice. Do not finalize a design with this information.<br />
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from<br />
published specifications. Current characterized errata are available on request.<br />
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.<br />
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-<br />
548-4725, or go to: http://www.intel.com/design/literature.htm.<br />
Intel<br />
®<br />
Virtualization Technology requires a computer system with an enabled Intel<br />
®<br />
processor, BIOS, virtual machine monitor (VMM). Functionality,<br />
performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all<br />
operating systems. Consult your PC manufacturer. For more information, visit: http://www.intel.com/go/virtualization.<br />
Intel<br />
®<br />
Turbo Boost Technology requires a system with Intel<br />
®<br />
Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology<br />
2.0 are only available on select Intel<br />
®<br />
processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system<br />
configuration. For more information, visit: http://www.intel.com/go/turbo.<br />
Intel<br />
®<br />
Hyper-Threading Technology requires an Intel<br />
®<br />
HT Technology enabled system, check with your PC manufacturer. Performance will vary<br />
depending on the specific hardware and software used. Not available on Intel<br />
®<br />
Core™ i5-750. For more information including details on which<br />
processors support HT Technology, visit http://www.intel.com/info/hyperthreading.<br />
Intel<br />
®<br />
64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific<br />
hardware and software you use. Consult your PC manufacturer for more information. For more information, visit: http://www.intel.com/info/em64t.<br />
Intel, Intel Core, Pentium, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.<br />
*Other names and brands may be claimed as the property of others.<br />
Copyright © 2012, Intel Corporation. All rights reserved.<br />
Contents<br />
Specification Update 3<br />
Contents<br />
Revision History...............................................................................................................5<br />
Preface ..............................................................................................................................6<br />
Summary Tables of Changes..........................................................................................8<br />
Identification Information ..............................................................................................13<br />
Errata...............................................................................................................................16<br />
Specification Changes...................................................................................................42<br />
Specification Clarifications ...........................................................................................43<br />
Documentation Changes...............................................................................................44<br />
§ §Contents<br />
4 Specification Update<br />
Specification Update 5<br />
Revision History<br />
Revision Description Date<br />
001 • Initial Release. April 2012<br />
002<br />
• Added Errata BV68–BV83<br />
• Updated Processor Identification Table<br />
May 2012<br />
003<br />
• Added L-1 and N-0 steppings to errata summary table<br />
• Added L-1 and N-0 steppings to Component Identification using Programming<br />
Interface table<br />
• Updated Processor Identification Table<br />
June 2012<br />
004 • Added errata BV84-BV87 June 20126 Specification Update<br />
Preface<br />
This document is an update to the specifications contained in the Affected Documents<br />
table below. This document is a compilation of device and documentation errata,<br />
specification clarifications and changes. It is intended for hardware system<br />
manufacturers and software developers of applications, operating systems, or tools.<br />
Information types defined in Nomenclature are consolidated into the specification<br />
update and are no longer published in other documents.<br />
This document may also contain information that was not previously published.<br />
Affected Documents<br />
Related Documents<br />
Document Title Document Number<br />
Desktop 3rd Generation Intel® Core™ Processor Family Datasheet, Volume 1 326764-002<br />
Desktop 3rd Generation Intel®<br />
Core™ Processor Family Datasheet, Volume 2 326765-001<br />
Document Title<br />
Document Number/<br />
Location<br />
AP-485, Intel®<br />
Processor Identification and the CPUID Instruction http://www.intel.com/<br />
design/processor/<br />
applnots/241618.htm<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual,<br />
Volume 1: Basic Architecture<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual,<br />
Volume 2A: Instruction Set Reference Manual A-M<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual,<br />
Volume 2B: Instruction Set Reference Manual N-Z<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual,<br />
Volume 3A: System Programming Guide<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual,<br />
Volume 3B: System Programming Guide<br />
Intel®<br />
64 and IA-32 Intel Architecture Optimization Reference<br />
Manual<br />
http://www.intel.com/<br />
products/processor/<br />
manuals/index.htm<br />
Intel®<br />
64 and IA-32 Architectures Software Developer’s Manual<br />
Documentation Changes<br />
http://www.intel.com/<br />
design/processor/<br />
specupdt/252046.htm<br />
ACPI Specifications www.acpi.info<br />
Specification Update 7<br />
Nomenclature<br />
Errata are design defects or errors. These may cause the processor behavior to<br />
deviate from published specifications. Hardware and software designed to be used with<br />
any given stepping must assume that all errata documented for that stepping are<br />
present on all devices.<br />
S-Spec Number is a five-digit code used to identify products. Products are<br />
differentiated by their unique characteristics such as, core speed, L2 cache size,<br />
package type, etc. as described in the processor identification information table. Read<br />
all notes associated with each S-Spec number.<br />
Specification Changes are modifications to the current published specifications.<br />
These changes will be incorporated in any new release of the specification.<br />
Specification Clarifications describe a specification in greater detail or further<br />
highlight a specification’s impact to a complex design situation. These clarifications will<br />
be incorporated in any new release of the specification.<br />
Documentation Changes include typos, errors, or omissions from the current<br />
published specifications. These will be incorporated in any new release of the<br />
specification.<br />
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a<br />
particular stepping is no longer commercially available. Under these circumstances,<br />
errata removed from the specification update are archived and available upon request.<br />
Specification changes, specification clarifications and documentation changes are<br />
removed from the specification update when the appropriate changes are made to the<br />
appropriate product specification or user documentation (datasheets, manuals, and so<br />
on).8 Specification Update<br />
Summary Tables of Changes<br />
The following tables indicate the errata, specification changes, specification<br />
clarifications, or documentation changes which apply to the processor. Intel may fix<br />
some of the errata in a future stepping of the component, and account for the other<br />
outstanding issues through documentation or specification changes as noted. These<br />
tables uses the following notations:<br />
Codes Used in Summary Tables<br />
Stepping<br />
X: Errata exists in the stepping indicated. Specification Change or<br />
Clarification that applies to this stepping.<br />
(No mark)<br />
or (Blank box): This erratum is fixed in listed stepping or specification change<br />
does not apply to listed stepping.<br />
Page<br />
(Page): Page location of item in this document.<br />
Status<br />
Doc: Document change or update will be implemented.<br />
Plan Fix: This erratum may be fixed in a future stepping of the product.<br />
Fixed: This erratum has been previously fixed.<br />
No Fix: There are no plans to fix this erratum.<br />
Row<br />
Change bar to left of a table row indicates this erratum is either new or modified from<br />
the previous version of the document.<br />
Specification Update 9<br />
Errata (Sheet 1 of 4)<br />
Number<br />
Steppings<br />
Status ERRATA<br />
E-1 L-1 N-0<br />
BV1 X X X No Fix The Processor May Report a #TS Instead of a #GP Fault<br />
BV2 X X X No Fix<br />
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page<br />
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or<br />
Lead to Memory-Ordering Violations.<br />
BV3 X X X No Fix IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly<br />
BV4 X X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values<br />
BV5 X X X No Fix<br />
IRET under Certain Conditions May Cause an Unexpected Alignment Check<br />
Exception<br />
BV6 X X X No Fix<br />
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some<br />
Transitions<br />
BV7 X X X No Fix<br />
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be<br />
Preempted<br />
BV8 X X X No Fix<br />
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs<br />
in 64-bit Mode<br />
BV9 X X X No Fix<br />
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/<br />
XRSTOR Image Leads to Partial Memory Update<br />
BV10 X X X No Fix Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM<br />
BV11 X X X No Fix<br />
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a<br />
Translation Change<br />
BV12 X X X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set<br />
BV13 X X X No Fix<br />
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB<br />
Error<br />
BV14 X X X No Fix<br />
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled<br />
Breakpoints<br />
BV15 X X X No Fix LER MSRs May Be Unreliable<br />
BV16 X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI<br />
BV17 X X X No Fix PEBS Record not Updated when in Probe Mode<br />
BV18 X X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang<br />
BV19 X X X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word<br />
BV20 X X X No Fix<br />
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a<br />
System Hang<br />
BV21 X X X No Fix<br />
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not<br />
Provide Correct Exception Error Code<br />
BV22 X X X No Fix<br />
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is<br />
Followed by a Store or an MMX Instruction<br />
BV23 X X X No Fix APIC Error “Received Illegal Vector” May be Lost<br />
BV24 X X X No Fix<br />
Changing the Memory Type for an In-Use Page Translation May Lead to MemoryOrdering Violations<br />
BV25 X X X No Fix<br />
Reported Memory Type May Not Be Used to Access the VMCS and Referenced<br />
Data Structures<br />
BV26 X X X No Fix<br />
LBR, BTM or BTS Records May have Incorrect Branch From Information After an<br />
EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling10 Specification Update<br />
BV27 X X X No Fix<br />
Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation<br />
Descriptors<br />
BV28 X X X No Fix<br />
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which<br />
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode<br />
BV29 X X X No Fix<br />
VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported<br />
Field in VMCS<br />
BV30 X X X No Fix Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine<br />
BV31 X X X No Fix<br />
Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of<br />
as Critical Errors<br />
BV32 X X X No Fix<br />
Reception of Certain Malformed Transactions May Cause PCIe Port to Hang<br />
Rather Than Reporting an Error<br />
BV33 X X X No Fix Clock Modulation Duty Cycle Cannot be Programmed to 6.25%<br />
BV34 X X X No Fix Processor May Fail to Acknowledge a TLP Request<br />
BV35 X X X No Fix An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2<br />
BV36 X X X No Fix<br />
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain<br />
Conditions<br />
BV37 X X X No Fix PCIe* LTR Incorrectly Reported as Being Supported<br />
BV38 X X X No Fix<br />
PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have<br />
Occurred<br />
BV39 X X X No Fix<br />
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch<br />
Instructions<br />
BV40 X X X No Fix Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered<br />
BV41 X X X No Fix<br />
PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the<br />
Specification<br />
BV42 X X X No Fix<br />
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate<br />
with 32-bit Length Registers<br />
BV43 X X X No Fix<br />
Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter<br />
0<br />
BV44 X X X No Fix IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset<br />
BV45 X X X No Fix<br />
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is<br />
Followed by a REP MOVSB or STOSB<br />
BV46 X X X No Fix<br />
Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial<br />
Speed Upgrade<br />
BV47 X X X No Fix LTR Message is Not Treated as an Unsupported Request<br />
BV48 X X X No Fix<br />
64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI<br />
Before Any Data is Transferred<br />
BV49 X X X No Fix<br />
An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result<br />
EFLAGS.RF Being Incorrectly Set<br />
BV50 X X X No Fix<br />
Accessing Physical Memory Space 0-640K through the Graphics Aperture May<br />
Cause Unpredictable System Behavior<br />
BV51 X X X No Fix PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full<br />
BV52 X X X No Fix Instructions Retired Event May Over Count Execution of IRET Instructions<br />
BV53 X X X No Fix PCIe* Link May Unexpectedly Exit Loopback State<br />
Errata (Sheet 2 of 4)<br />
Number<br />
Steppings<br />
Status ERRATA<br />
E-1 L-1 N-0<br />
Specification Update 11<br />
BV54 X X X No Fix The RDRAND Instruction Will Not Execute as Expected<br />
BV55 X X X No Fix<br />
A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a<br />
System Hang<br />
BV56 X X X No Fix PCI Express* Gen3 Receiver Return Loss May Exceed Specifications<br />
BV57 X X X No Fix<br />
Direct Access Via VT-d to The Processor Graphics Device May Lead to a System<br />
Hang<br />
BV58 X X X No Fix<br />
An Event May Intervene Before a System Management Interrupt That Results from<br />
IN or INS<br />
BV59 X X X No Fix<br />
PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During<br />
Upconfiguration<br />
BV60 X X X No Fix<br />
The Processor May Not Comply With PCIe* Equalization Preset Reflection<br />
Requirements for 8 GT/s Mode of Operation<br />
BV61 X X X No Fix Processor May Issue PCIe* EIEOS at Incorrect Rate<br />
BV62 X X X No Fix<br />
Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe*<br />
5GT/s Speed<br />
BV63 X X X No Fix<br />
PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May<br />
be Incorrect<br />
BV64 X X X No Fix PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s<br />
BV65 X X X No Fix<br />
Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang<br />
Rather Than Reporting an Error<br />
BV66 X X X No Fix PCIe* Link Width May Degrade After a Warm Reset<br />
BV67 X X X No Fix MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate<br />
BV68 X X X No Fix PCIe* Link May Not Enter Loopback.Active When Directed<br />
BV69 X X X No Fix<br />
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for<br />
VEX.vvvv May Produce a #NM Exception<br />
BV70 X X X No Fix Unexpected #UD on VZEROALL/VZEROUPPER<br />
BV71 X X X No Fix PCIe* Root Port May Not Initiate Link Speed Change<br />
BV72 X X X No Fix Successive Fixed Counter Overflows May be Discarded<br />
BV73 X X X No Fix<br />
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM<br />
Exception<br />
BV74 X X X No Fix<br />
VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the<br />
Shutdown State<br />
BV75 X X X No Fix<br />
Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-<br />
Bit Linear Addresses<br />
BV76 X X X No Fix PCIe* Controller May Not Properly Indicate Link Electrical Idle Condition<br />
BV77 X X X No Fix PCIe* Controller May Not Enter Loopback<br />
BV78 X X X No Fix Link Margin Characterization May Hang Link<br />
BV79 X X X No Fix Unused PCIe* Lanes May Report Correctable Errors<br />
BV80 X X X No Fix RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information<br />
BV81 X X X No Fix PCIe* Link May Fail Link Width Upconfiguration<br />
BV82 X X X No Fix Graphics L3 Cache Parity Errors May Not be Detected<br />
Errata (Sheet 3 of 4)<br />
Number<br />
Steppings<br />
Status ERRATA<br />
E-1 L-1 N-012 Specification Update<br />
BV83 X X X No Fix<br />
A PCIe* Link That is in Link Disable State May Prevent DDR I/O Buffers From<br />
Entering a Power Gated State<br />
BV84 X X X No Fix REP MOVSB May Incorrectly Update ECX, ESI, and EDI<br />
BV85 X X X No Fix Performance-Counter Overflow Indication May Cause Undesired Behavior<br />
BV86 X X X No Fix RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result<br />
BV87 X X X No Fix VEX.L is Not Ignored with VCVT*2SI Instructions<br />
Errata (Sheet 4 of 4)<br />
Number<br />
Steppings<br />
Status ERRATA<br />
E-1 L-1 N-0<br />
Specification Changes<br />
Number SPECIFICATION CHANGES<br />
None for this revision of this specification update.<br />
Specification Clarifications<br />
Number SPECIFICATION CLARIFICATIONS<br />
None for this revision of this specification update.<br />
Documentation Changes<br />
Number DOCUMENTATION CHANGES<br />
None for this revision of this specification update.<br />
Specification Update 13<br />
Identification Information<br />
Component Identification using Programming Interface<br />
The processor stepping can be identified by the following register contents:<br />
Notes:<br />
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],<br />
to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,<br />
or Intel®<br />
Core™ processor family.<br />
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are<br />
used to identify the model of the processor within the processor’s family.<br />
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM<br />
processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor<br />
system).<br />
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX<br />
register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of<br />
the Device ID register accessible through Boundary Scan.<br />
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX<br />
register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the<br />
Device ID register accessible through Boundary Scan.<br />
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor<br />
stepping ID number in the CPUID information.<br />
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended<br />
Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID<br />
value in the EAX register. Note that the EDX processor signature value after reset is<br />
equivalent to the processor signature output value in the EAX register.<br />
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX<br />
registers after the CPUID instruction is executed with a 2 in the EAX register.<br />
The processor can be identified by the following register contents:<br />
Notes:<br />
1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00h–01h in the PCI<br />
function 0 configuration space.<br />
2. The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02h–<br />
03h in the PCI function 0 configuration space.<br />
3. The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at<br />
Device 2 offset 02h–03h in the PCI function 0 configuration space.<br />
4. The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI<br />
function 0 configuration space.<br />
Reserved<br />
Extended<br />
Family<br />
1<br />
Extended<br />
Model<br />
2 Reserved<br />
Processor<br />
Type<br />
3<br />
Family<br />
Code<br />
4<br />
Model<br />
Number<br />
5<br />
Stepping<br />
ID6<br />
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0<br />
00000000b 0011b 00b 0110 1010b xxxxb<br />
Stepping Vendor ID1<br />
Host Device ID2 Processor Graphics<br />
Device ID3 Revision ID4<br />
E-1 8086h 0150h 0162h 09h<br />
L-1 8086h 0150h 0162h 09h<br />
N-0 8086h 0150h 0152h 09h14 Specification Update<br />
Component Marking Information<br />
The processor stepping can be identified by the following component markings.<br />
Figure 1. Processor Production Top-side Markings (Example)<br />
Table 1. Processor Identification (Sheet 1 of 2)<br />
Number<br />
Processor<br />
Number<br />
Stepping<br />
Processor<br />
Signature<br />
Core Frequency<br />
(GHz) /<br />
DDR3 (MHz) /<br />
Processor<br />
Graphics<br />
Frequency<br />
Max Intel®<br />
Turbo Boost<br />
Technology<br />
2.0 Frequency<br />
(GHz)<br />
1<br />
Shared<br />
L3 Cache<br />
Size (MB)<br />
Notes<br />
SR0PQ i7-3770T E-1 000306A9h 2.5 / 1600 / 650<br />
4 core: 3.1<br />
3 core: 3.4<br />
2 core: 3.6<br />
1 core: 3.7<br />
8 2,3,4,5,6<br />
SR0PN i7-3770S E-1 000306A9h 3.1 / 1600 / 650<br />
4 core: 3.5<br />
3 core: 3.6<br />
2 core: 3.8<br />
1 core: 3.9<br />
8 2,3,4,5,6<br />
SR0PL i7-3770K E-1 000306A9h 3.5 / 1600 / 650<br />
4 core: 3.7<br />
3 core: 3.8<br />
2 core: 3.9<br />
1 core: 3.9<br />
8 2,4,6<br />
SR0PK i7-3770 E-1 000306A9h 3.4 / 1600 / 650<br />
4 core: 3.7<br />
3 core: 3.8<br />
2 core: 3.9<br />
1 core: 3.9<br />
8 2,3,4,5,6<br />
SR0P1 i5-3570T E-1 000306A9h 2.3 / 1600 / 650<br />
4 core: 2.9<br />
3 core: 3<br />
2 core: 3.2<br />
1 core: 3.3<br />
6 3,4,5,6<br />
LOT NO S/N<br />
i ©'10<br />
BRAND PROC#<br />
SLxxx SPEED<br />
[COO]<br />
[FPO]<br />
M<br />
e4<br />
Specification Update 15<br />
Notes:<br />
1. This column indicates maximum Intel® Turbo Boost Technology 2.0 frequency (GHz) for 4,3, 2 or 1<br />
cores active respectively.<br />
2. Intel®<br />
Hyper-Threading Technology enabled.<br />
3. Intel® Trusted Execution Technology (Intel® TXT) enabled.<br />
4. Intel®<br />
Virtualization Technology for IA-32, Intel®<br />
64 and Intel®<br />
Architecture (Intel®<br />
VT-x) enabled.<br />
5. Intel®<br />
Virtualization Technology for Directed I/O (Intel®<br />
VT-d) enabled.<br />
6. Intel® AES-NI enabled.<br />
SR0P3 i5-3550S E-1 000306A9h 3 / 1600 / 650<br />
4 core: 3.3<br />
3 core: 3.4<br />
2 core: 3.6<br />
1 core: 3.7<br />
6 3,4,5,6<br />
SR0PM i5-3570K E-1 000306A9h 3.4 / 1600 / 650<br />
4 core: 3.6<br />
3 core: 3.7<br />
2 core: 3.8<br />
1 core: 3.8<br />
6 4,6<br />
SR0P0 i5-3550 E-1 000306A9h 3.3 / 1600 / 650<br />
4 core: 3.5<br />
3 core: 3.6<br />
2 core: 3.7<br />
1 core: 3.7<br />
6 3,4,5,6<br />
SR0PP i5-3475S E-1 000306A9h 2.9 / 1600 / 650<br />
4 core: 3.2<br />
3 core: 3.3<br />
2 core: 3.5<br />
1 core: 3.6<br />
6 3,4,5,6<br />
SR0P2 i5-3450S E-1 000306A9h 2.8 / 1600 / 650<br />
4 core: 3.1<br />
3 core: 3.2<br />
2 core: 3.4<br />
1 core: 3.5<br />
6 4,6<br />
SR0PF i5-3450 E-1 000306A9h 3.1 / 1600 / 650<br />
4 core: 3.3<br />
3 core: 3.4<br />
2 core: 3.5<br />
1 core: 3.5<br />
6 4,6<br />
SR0T9 i5-3570S N-0 000306A9h 3.1 / 1600 / 650<br />
4 core: 3.4<br />
3 core: 3.5<br />
2 core: 3.7<br />
1 core: 3.8<br />
6 3,4,5,6<br />
SR0T7 i5-3570 N-0 000306A9h 3.4 / 1600 / 650<br />
4 core: 3.6<br />
3 core: 3.7<br />
2 core: 3.8<br />
1 core: 3.8<br />
6 3,4,5,6<br />
SR0TA i5-3470S N-0 000306A9h 2.9 / 1600 / 650<br />
4 core: 3.2<br />
3 core: 3.3<br />
2 core: 3.5<br />
1 core: 3.6<br />
6 3,4,5,6<br />
SR0T8 i5-3470 N-0 000306A9h 3.2 / 1600 / 650<br />
4 core: 3.4<br />
3 core: 3.5<br />
2 core: 3.6<br />
1 core: 3.6<br />
6 3,4,5,6<br />
SR0RJ i5-3470T L-1 000306A9h 2.9 / 1600 / 650<br />
4 core: 0<br />
3 core: 0<br />
2 core: 3.3<br />
1 core: 3.6<br />
3 2,3,4,5,6<br />
Table 1. Processor Identification (Sheet 2 of 2)<br />
Number<br />
Processor<br />
Number<br />
Stepping<br />
Processor<br />
Signature<br />
Core Frequency<br />
(GHz) /<br />
DDR3 (MHz) /<br />
Processor<br />
Graphics<br />
Frequency<br />
Max Intel®<br />
Turbo Boost<br />
Technology<br />
2.0 Frequency<br />
(GHz)<br />
1<br />
Shared<br />
L3 Cache<br />
Size (MB)<br />
Notes16 Specification Update<br />
Errata<br />
BV1. The Processor May Report a #TS Instead of a #GP Fault<br />
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)<br />
instead of a #GP fault (general protection exception).<br />
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP<br />
fault. Intel has not observed this erratum with any commercially available software.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing<br />
Page Boundaries with Inconsistent Memory Types may use an<br />
Incorrect Data Size or Lead to Memory-Ordering Violations.<br />
Problem: Under certain conditions as described in the Software Developers Manual section “Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family<br />
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this<br />
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from<br />
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data<br />
size or may observe memory ordering violations.<br />
Implication: Upon crossing the page boundary the following may occur, dependent on the new page<br />
memory type:<br />
• UC the data size of each write will now always be 8 bytes, as opposed to the<br />
original data size.<br />
• WP the data size of each write will now always be 8 bytes, as opposed to the<br />
original data size and there may be a memory ordering violation.<br />
• WT there may be a memory ordering violation.<br />
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,<br />
WP or WT memory type within a single REP MOVS or REP STOS instruction that will<br />
execute with fast strings enabled.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV3. IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly<br />
Problem: The IO_SMI bit in SMRAM’s location 7FA4H is set to "1" by the CPU to indicate a System<br />
Management Interrupt (SMI) occurred as the result of executing an instruction that<br />
reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:<br />
• A non-I/O instruction<br />
• SMI is pending while a lower priority event interrupts<br />
• A REP I/O read<br />
• A I/O read that redirects to MWAIT<br />
Implication: SMM handlers may get false IO_SMI indication.<br />
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was<br />
triggered by an instruction that read from an I/O port. The SMM handler must not<br />
restart an I/O instruction if the platform has not been configured to generate a<br />
synchronous SMI for the recorded I/O port address.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 17<br />
BV4. Performance Monitor SSE Retired Instructions May Return Incorrect<br />
Values<br />
Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track<br />
retired SSE instructions. Due to this erratum, the processor may also count other types<br />
of instructions resulting in higher than expected values.<br />
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than<br />
expected.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV5. IRET under Certain Conditions May Cause an Unexpected Alignment<br />
Check Exception<br />
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET<br />
instruction even though alignment checks were disabled at the start of the IRET. This<br />
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs<br />
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the<br />
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e<br />
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. <br />
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if<br />
alignment checks are disabled at the start of the IRET. This erratum can only be<br />
observed with a software generated stack frame.<br />
Workaround: Software should not generate misaligned stack frames for use with IRET.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV6. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not<br />
Count Some Transitions<br />
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts<br />
transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if<br />
only a small number of MMX instructions (including EMMS) are executed immediately<br />
after the last FP instruction, a FP to MMX transition may not be counted.<br />
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be<br />
lower than expected. The degree of undercounting is dependent on the occurrences of<br />
teption). Intel has not observed this erratum with any commercially available software.<br />
Workaround: None identified<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes<br />
May be Preempted<br />
Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a<br />
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP<br />
fault may be preempted by another lower priority fault (e.g. Page Fault (#PF)).<br />
However, if the preempting lower priority faults are resolved by the operating system<br />
and the instruction retried, a #GP fault will occur.<br />
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault. <br />
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are<br />
placed before the instruction.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.18 Specification Update<br />
BV8. LBR, BTS, BTM May Report a Wrong Address when an Exception/<br />
Interrupt Occurs in 64-bit Mode<br />
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),<br />
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,<br />
during a specific boundary condition where the exception/interrupt occurs right after<br />
the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)<br />
in 64-bit mode, the LBR return registers will save a wrong return address with bits 63<br />
to 48 incorrectly sign extended to all 1’s. Subsequent BTS and BTM operations which<br />
report the LBR will also be incorrect.<br />
Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/<br />
interrupt.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV9. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or<br />
XSAVE/XRSTOR Image Leads to Partial Memory Update<br />
Problem: A partial memory state save of the FXSAVE or XSAVE image or a partial memory state<br />
restore of the FXRSTOR or XRSTOR image may occur if a memory address exceeds the<br />
64KB limit while the processor is operating in 16-bit mode or if a memory address<br />
exceeds the 4GB limit while the processor is operating in 32-bit mode.<br />
Implication: FXSAVE/FXRSTOR or XSAVE/XRSTOR will incur a #GP fault due to the memory limit<br />
violation as expected but the memory state may be only partially saved or restored.<br />
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and<br />
32-bit mode memory limits.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV10. Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM<br />
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update<br />
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their<br />
data invalid. The corresponding data if sent out as a BTM on the system bus will also be<br />
incorrect. Note: This issue would only occur when one of the 3 above mentioned debug<br />
support facilities are used.<br />
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be<br />
used.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 19<br />
BV11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits<br />
after a Translation Change<br />
Problem: This erratum is regarding the case where paging structures are modified to change a<br />
linear address from writable to non-writable without software performing an<br />
appropriate TLB invalidation. When a subsequent access to that address by a specific<br />
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,<br />
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPTinduced VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag<br />
values that the EFLAGS register would have held had the instruction completed without<br />
fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if<br />
its delivery causes a nested fault.<br />
Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or<br />
an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not<br />
identified software that is affected by this erratum. This erratum will have no further<br />
effects once the original instruction is restarted because the instruction will produce the<br />
same results as if it had initially completed without fault or VM exit.<br />
Workaround: If the handler of the affected events inspects the arithmetic portion of the saved<br />
EFLAGS value, then system software should perform a synchronized paging structure<br />
modification and TLB invalidation.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV12. B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set<br />
Problem: Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may be<br />
incorrectly set for non-enabled breakpoints when the following sequence happens:<br />
1. MOV or POP instruction to SS (Stack Segment) selector;<br />
2. Next instruction is FP (Floating Point) that gets FP assist<br />
3. Another instruction after the FP instruction completes successfully<br />
4. A breakpoint occurs due to either a data breakpoint on the preceding instruction or<br />
a code breakpoint on the next instruction.<br />
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be<br />
reported in B0-B3 after the breakpoint occurs in step 4.<br />
Implication: Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-enabled<br />
breakpoints.<br />
Workaround: Software should not execute a floating point instruction directly after a MOV SS or POP<br />
SS instruction.<br />
Status: For the steppings affected, see the Summary Tables of Changes.20 Specification Update<br />
BV13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance<br />
of a DTLB Error<br />
Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the<br />
Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error<br />
code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status<br />
register.<br />
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate<br />
indication of multiple occurrences of DTLB errors. There is no other impact to normal<br />
processor functionality.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV14. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled<br />
Breakpoints<br />
Problem: When a debug exception is signaled on a load that crosses cache lines with data<br />
forwarded from a store and whose corresponding breakpoint enable flags are disabled<br />
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.<br />
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the<br />
corresponding breakpoint enable flag in DR7 is disabled.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV15. LER MSRs May Be Unreliable<br />
Problem: Due to certain internal processor events, updates to the LER (Last Exception Record)<br />
MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when<br />
no update was expected.<br />
Implication: The values of the LER MSRs may be unreliable.<br />
Workaround: None Identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV16. Storage of PEBS Record Delayed Following Execution of MOV SS or STI<br />
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based<br />
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS<br />
buffer. The information in the PEBS record represents the state of the next instruction<br />
to be executed following the counter overflow. Due to this erratum, if the counter<br />
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is<br />
delayed by one instruction.<br />
Implication: When this erratum occurs, software may observe storage of the PEBS record being<br />
delayed by one instruction following execution of MOV SS or STI. The state information<br />
in the PEBS record will also reflect the one instruction delay.<br />
Workaround: None identified.<br />
Specification Update 21<br />
BV17. PEBS Record not Updated when in Probe Mode<br />
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based<br />
Sampling), overflows of the counter can result in storage of a PEBS record in the PEBS<br />
buffer. Due to this erratum, if the overflow occurs during probe mode, it may be<br />
ignored and a new PEBS record may not be added to the PEBS buffer.<br />
Implication: Due to this erratum, the PEBS buffer may not be updated by overflows that occur<br />
during probe mode.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV18. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in<br />
Hang<br />
Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local<br />
xAPIC's address space, the processor will hang.<br />
Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space<br />
must be uncached. The MONITOR instruction only functions correctly if the specified<br />
linear address range is of the type write-back. CLFLUSH flushes data from the cache.<br />
Intel has not observed this erratum with any commercially available software.<br />
Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV19. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word<br />
Problem: Under a specific set of conditions, MMX stores (MOVD, MOVQ, MOVNTQ, MASKMOVQ)<br />
which cause memory access faults (#GP, #SS, #PF, or #AC), may incorrectly update<br />
the x87 FPU tag word register.<br />
This erratum will occur when the following additional conditions are also met.<br />
• The MMX store instruction must be the first MMX instruction to operate on x87 FPU<br />
state (i.e. the x87 FP tag word is not already set to 0x0000).<br />
• For MOVD, MOVQ, MOVNTQ stores, the instruction must use an addressing mode<br />
that uses an index register (this condition does not apply to MASKMOVQ).<br />
Implication: If the erratum conditions are met, the x87 FPU tag word register may be incorrectly set<br />
to a 0x0000 value when it should not have been modified.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV20. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also<br />
Result in a System Hang<br />
Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a<br />
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in<br />
another machine check bank (IA32_MCi_STATUS).<br />
Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang<br />
and an Internal Timer Error to be logged.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.22 Specification Update<br />
BV21. #GP on Segment Selector Descriptor that Straddles Canonical<br />
Boundary May Not Provide Correct Exception Error Code<br />
Problem: During a #GP (General Protection Exception), the processor pushes an error code on to<br />
the exception handler’s stack. If the segment selector descriptor straddles the<br />
canonical boundary, the error code pushed onto the stack may be incorrect.<br />
Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this<br />
erratum with any commercially available software.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV22. DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP<br />
SS is Followed by a Store or an MMX Instruction<br />
Problem: Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not<br />
cause a debug exception immediately after MOV/POP SS but will be delayed until the<br />
instruction boundary following the next instruction is reached. After the debug<br />
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints<br />
matched during the MOV/POP SS as well as breakpoints detected by the following<br />
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about<br />
data breakpoints matched during the MOV/POP SS when the following instruction is<br />
either an MMX instruction that uses a memory addressing mode with an index or a<br />
store instruction.<br />
Implication: When this erratum occurs, DR6 may not contain information about all breakpoints<br />
matched. This erratum will not be observed under the recommended usage of the MOV<br />
SS,r/m or POP SS instructions (i.e., following them only with an instruction that writes<br />
(E/R)SP).<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV23. APIC Error “Received Illegal Vector” May be Lost<br />
Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error<br />
Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error<br />
is received on the same internal clock that the ESR is being written (as part of the<br />
write-read ESR access flow). The corresponding error interrupt will also not be<br />
generated for this case.<br />
Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR<br />
properly and may not generate an error interrupt.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 23<br />
BV24. Changing the Memory Type for an In-Use Page Translation May Lead<br />
to Memory-Ordering Violations<br />
Problem: Under complex microarchitectural conditions, if software changes the memory type for<br />
data being actively used and shared by multiple threads without the use of semaphores<br />
or barriers, software may see load operations execute out of order.<br />
Implication: Memory ordering may be violated. Intel has not observed this erratum with any<br />
commercially available software.<br />
Workaround: Software should ensure pages are not being actively used before requesting their<br />
memory type be changed.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV25. Reported Memory Type May Not Be Used to Access the VMCS and<br />
Referenced Data Structures<br />
Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor<br />
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due<br />
to this erratum, a VMX access to the VMCS or referenced data structures will instead<br />
use the memory type that the MTRRs (memory-type range registers) specify for the<br />
physical address of the access.<br />
Implication: Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type<br />
will be used but the processor may use a different memory type.<br />
Workaround: Software should ensure that the VMCS and referenced data structures are located at<br />
physical addresses that are mapped to WB memory type by the MTRRs.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV26. LBR, BTM or BTS Records May have Incorrect Branch From<br />
Information After an EIST/T-state/S-state/C1E Transition or Adaptive<br />
Thermal Throttling<br />
Problem: The “From” address associated with the LBR (Last Branch Record), BTM (Branch Trace<br />
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after a<br />
transition of:<br />
• EIST (Enhanced Intel® SpeedStep Technology)<br />
• T-state (Thermal Monitor states)<br />
• S1-state (ACPI package sleep state)<br />
• C1E (Enhanced C1 Low Power state)<br />
• Adaptive Thermal Throttling<br />
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch<br />
“From” addresses for the first branch after a transition of EIST, T-states, S-states, C1E,<br />
or Adaptive Thermal Throttling.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.24 Specification Update<br />
BV27. Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued<br />
Invalidation Descriptors<br />
Problem: Reserved bits in the Queued Invalidation descriptors of Intel VT-d (Virtualization<br />
Technology for Directed I/O) are expected to be zero, meaning that software must<br />
program them as zero while the processor checks if they are not zero. Upon detection<br />
of a non-zero bit in a reserved field an Intel VT-d fault should be recorded. Due to this<br />
erratum the processor does not check reserved bit values for Queued Invalidation<br />
descriptors.<br />
Implication: Due to this erratum, faults will not be reported when writing to reserved bits of Intel<br />
VT-d Queued Invalidation Descriptors.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV28. FP Data Operand Pointer May Be Incorrectly Calculated After an FP<br />
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit<br />
Address Size in 64-bit Mode<br />
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand<br />
associated with the last non-control FP instruction executed by the processor. If an 80-<br />
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory<br />
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the<br />
value contained in the FP Data Operand Pointer may be incorrect.<br />
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit<br />
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.<br />
Intel has not observed this erratum with any commercially available software.<br />
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code<br />
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses<br />
are wrapped around a 4-Gbyte boundary.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV29. VMREAD/VMWRITE Instruction May Not Fail When Accessing an<br />
Unsupported Field in VMCS<br />
Problem: The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B states<br />
that execution of VMREAD or VMWRITE should fail if the value of the instruction’s<br />
register source operand corresponds to an unsupported field in the VMCS (Virtual<br />
Machine Control Structure). The correct operation is that the logical processor will set<br />
the ZF (Zero Flag), write 0CH into the VM-instruction error field and for VMREAD leave<br />
the instruction’s destination operand unmodified. Due to this erratum, the instruction<br />
may instead clear the ZF, leave the VM-instruction error field unmodified and for<br />
VMREAD modify the contents of its destination operand.<br />
Implication: Accessing an unsupported field in VMCS will fail to properly report an error. In addition,<br />
VMREAD from an unsupported VMCS field may unexpectedly change its destination<br />
operand. Intel has not observed this erratum with any commercially available software.<br />
Workaround: Software should avoid accessing unsupported fields in a VMCS.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 25<br />
BV30. Spurious Interrupts May be Generated From the Intel® VT-d Remap<br />
Engine<br />
Problem: If software clears the F (Fault) bit 127 of the Fault Recording Register (FRCD_REG at<br />
offset 0x208 in Remap Engine BAR) by writing 1b through RW1C command (Read Write<br />
1 to Clear) when the F bit is already clear then a spurious interrupt from Intel VT-d<br />
(Virtualization Technology for Directed I/O ) Remap Engine may be observed.<br />
Implication: Due to this erratum, spurious interrupts will occur from the Intel VT-d Remap Engine<br />
following RW1C clearing F bit.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV31. Malformed PCIe Transactions May be Treated as Unsupported<br />
Requests Instead of as Critical Errors<br />
Problem: PCIe MSG/MSG_D TLPs (Transaction Layer Packets) with incorrect Routing Code as well<br />
as the deprecated TCfgRD and TCfgWr types should be treated as malformed<br />
transactions leading to a critical error. Due to this erratum, the integrated PCIe<br />
controller's root ports may treat such messages as UR (Unsupported Requests).<br />
Implication: Legacy malformed PCIe transactions may be treated as UR instead of as critical errors.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV32. Reception of Certain Malformed Transactions May Cause PCIe Port to<br />
Hang Rather Than Reporting an Error<br />
Problem: If the processor receives an upstream malformed non posted packet for which the type<br />
field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then<br />
due to this erratum the integrated PCIe controller may hang instead of reporting the<br />
malformed packet error or issuing an unsupported request completion transaction.<br />
Implication: Due to this erratum, the processor may hang without reporting errors when receiving a<br />
malformed PCIe transaction. Intel has not observed this erratum with any commercially<br />
available device.<br />
Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported<br />
requests with 4 DW header formats.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV33. Clock Modulation Duty Cycle Cannot be Programmed to 6.25%<br />
Problem: When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH)<br />
bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the<br />
expected 6.25% ratio.<br />
Implication: Due to this erratum, it is not possible to program the clock modulation to a 6.25% duty<br />
cycle.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.26 Specification Update<br />
BV34. Processor May Fail to Acknowledge a TLP Request<br />
Problem: When a PCIe root port’s receiver is in Receiver L0s power state and the port initiates a<br />
Recovery event, it will issue Training Sets to the link partner. The link partner will<br />
respond by initiating an L0s exit sequence. Prior to transmitting its own Training Sets,<br />
the link partner may transmit a TLP (Transaction Layer Packet) request. Due to this<br />
erratum, the root port may not acknowledge the TLP request.<br />
Implication: After completing the Recovery event, the PCIe link partner will replay the TLP request.<br />
The link partner may set a Correctable Error status bit, which has no functional effect.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV35. An Unexpected PMI May Occur After Writing a Large Value to<br />
IA32_FIXED_CTR2<br />
Problem: If the fixed-function performance counter IA32_FIXED_CTR2 MSR (30BH) is configured<br />
to generate a performance-monitor interrupt (PMI) on overflow and the counter’s value<br />
is greater than FFFFFFFFFFC0H, then this erratum may incorrectly cause a PMI if<br />
software performs a write to this counter.<br />
Implication: A PMI may be generated unexpectedly when programming IA32_FIXED_CTR2. Other<br />
than the PMI, the counter programming is not affected by this erratum as the<br />
attempted write operation does succeed.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV36. A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in<br />
Certain Conditions<br />
Problem: Under specific internal conditions, if software tries to write the IA32_FIXED_CTR1 MSR<br />
(30AH) a value that has all bits [31:1] set while the counter was just about to overflow<br />
when the write is attempted (i.e. its value was 0xFFFF FFFF FFFF), then due to this<br />
erratum the new value in the MSR may be corrupted.<br />
Implication: Due to this erratum, IA32_FIXED_CTR1 MSR may be written with a corrupted value.<br />
Workaround: Software may avoid this erratum by writing zeros to the IA32_FIXED_CTR1 MSR,<br />
before the desired write operation.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV37. PCIe* LTR Incorrectly Reported as Being Supported<br />
Problem: LTR (Latency Tolerance Reporting) is a new optional feature specified in PCIe rev. 2.1.<br />
The processor reports LTR as supported in LTRS bit in DCAP2 register (bus 0; Device 1;<br />
Function 0; offset 0xc4), but this feature is not supported.<br />
Implication: Due to this erratum, LTR is always reported as supported by the LTRS bit in the DCAP2<br />
register.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 27<br />
BV38. PerfMon Overflow Status Can Not be Cleared After Certain Conditions<br />
Have Occurred<br />
Problem: Under very specific timing conditions, if software tries to disable a PerfMon counter<br />
through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter eventselect (e.g. MSR 0x186) and the counter reached its overflow state very close to that<br />
time, then due to this erratum the overflow status indication in MSR<br />
IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.<br />
Implication: Due to this erratum, software may be unable to clear the PerfMon counter overflow<br />
status indication.<br />
Workaround: Software may avoid this erratum by clearing the PerfMon counter value prior to<br />
disabling it and then clearing the overflow status indication bit.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV39. #GP May be Signaled When Invalid VEX Prefix Precedes Conditional<br />
Branch Instructions<br />
Problem: When a 2-byte opcode of a conditional branch (opcodes 0F8xH, for any value of x)<br />
instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it<br />
may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of a<br />
#UD (illegal opcode) fault.<br />
Implication: Due to this erratum, #GP fault instead of a #UD may be signaled on an illegal<br />
instruction.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV40. Interrupt From Local APIC Timer May Not Be Detectable While Being<br />
Delivered<br />
Problem: If the local-APIC timer’s CCR (current-count register) is 0, software should be able to<br />
determine whether a previously generated timer interrupt is being delivered by first<br />
reading the delivery-status bit in the LVT timer register and then reading the bit in the<br />
IRR (interrupt-request register) corresponding to the vector in the LVT timer register. If<br />
both values are read as 0, no timer interrupt should be in the process of being<br />
delivered. Due to this erratum, a timer interrupt may be delivered even if the CCR is 0<br />
and the LVT and IRR bits are read as 0. This can occur only if the DCR (Divide<br />
Configuration Register) is greater than or equal to 4. The erratum does not occur if<br />
software writes zero to the Initial Count Register before reading the LVT and IRR bits.<br />
Implication: Software that relies on reads of the LVT and IRR bits to determine whether a timer<br />
interrupt is being delivered may not operate properly.<br />
Workaround: Software that uses the local-APIC timer must be prepared to handle the timer<br />
interrupts, even those that would not be expected based on reading CCR and the LVT<br />
and IRR bits; alternatively, software can avoid the problem by writing zero to the Initial<br />
Count Register before reading the LVT and IRR bits.<br />
Status: For the steppings affected, see the Summary Tables of Changes.28 Specification Update<br />
BV41. PCI Express<br />
*<br />
Differential Peak-Peak Tx Voltage Swing May Violate the<br />
Specification<br />
Problem: Under certain conditions, including extreme voltage and temperature, the peak-peak<br />
voltage may be higher than the specification.<br />
Implication: Violation of PCI Express® Base Specification of the VTX--DIFF-PP voltage. No failures<br />
have been observed due to this erratum.<br />
Workaround: None identified.<br />
BV42. PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always<br />
Operate with 32-bit Length Registers<br />
Problem: In 64-bit mode, using REX.W=1 with PCMPESTRI and PCMPESTRM or VEX.W=1 with<br />
VPCMPESTRI and VPCMPESTRM should support a 64-bit length operation with RAX/<br />
RDX. Due to this erratum, the length registers are incorrectly interpreted as 32-bit<br />
values.<br />
Implication: Due to this erratum, using REX.W=1 with PCMPESTRI and PCMPESTRM as well as<br />
VEX.W=1 with VPCMPESTRI and VPCMPESTRM do not result in promotion to 64-bit<br />
length registers.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV43. Multiple Performance Monitor Interrupts are Possible on Overflow of<br />
Fixed Counter 0<br />
Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon<br />
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on<br />
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum<br />
occurs.<br />
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and<br />
counter are configured as follows:<br />
• Intel®<br />
Hyper-Threading Technology is enabled<br />
• IA32_FIXED_CTR0 local and global controls are enabled<br />
• IA32_FIXED_CTR0 is set to count events only on its own thread<br />
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0).<br />
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = ‘1)<br />
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = ‘1)<br />
Implication: When this erratum occurs there may be multiple PMIs observed when<br />
IA32_FIXED_CTR0 overflows.<br />
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H)<br />
bit [12].<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 29<br />
BV44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset<br />
Problem: IA32_FEATURE_CONTROL MSR (3Ah) may have random values after RESET (including<br />
the reserved and Lock bits), and the read-modify-write of the reserved bits and/or the<br />
Lock bit being incorrectly set may cause an unexpected GP fault.<br />
Implication: Due to this erratum, an unexpected GP fault may occur and BIOS may not complete<br />
initialization.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV45. DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP<br />
SS is Followed by a REP MOVSB or STOSB<br />
Problem: Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not<br />
cause a debug exception immediately after MOV/POP SS but will be delayed until the<br />
instruction boundary following the next instruction is reached. After the debug<br />
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints<br />
matched during the MOV/POP SS as well as breakpoints detected by the following<br />
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about<br />
data breakpoints matched during the MOV/POP SS when the following instruction is<br />
either an REP MOVSB or REP STOSB.<br />
Implication: When this erratum occurs, DR6 may not contain information about all breakpoints<br />
matched. This erratum will not be observed under the recommended usage of the MOV<br />
SS,r/m or POP SS instructions (i.e., following them only with an instruction that writes<br />
(E/R)SP).<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV46. Setting Hardware Autonomous Speed Disable Configuration Bit Will<br />
Block Initial Speed Upgrade<br />
Problem: The PCI Express* Base Specification Revision 3.0 states that the Hardware<br />
Autonomous Speed Disable bit (Link Control Register 2, bit 5) does not block the initial<br />
transition to the highest supported common link speed. Setting this bit will block all<br />
autonomous speed changes.<br />
Implication: Due to this erratum, if the Hardware Autonomous Speed Disable bit is set, a given PCIe<br />
link may remain at 2.5 GT/s transfer rate. This erratum has not been observed with any<br />
commercially available add-in cards.<br />
Workaround: It is possible for software to initiate a directed speed change.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV47. LTR Message is Not Treated as an Unsupported Request<br />
Problem: The PCIe* root port does not support LTR (Latency Tolerance Reporting) capability.<br />
However, a received LTR message is not treated as a UR (Unsupported Request).<br />
Implication: Due to this erratum, an LTR message does not generate a UR error.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.30 Specification Update<br />
BV48. 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI<br />
And RSI Before Any Data is Transferred<br />
Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an address size of 32 bits, and<br />
if an interrupt is being recognized at the start of the instruction operation, the upper<br />
32-bits of RCX, RDI and RSI may be cleared, even though no data has yet been copied<br />
or written.<br />
Implication: Due to this erratum, the upper 32-bits of RCX, RDI and RSI may be prematurely<br />
cleared.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV49. An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB<br />
May Result EFLAGS.RF Being Incorrectly Set<br />
Problem: If a REP MOVSB/STOSB is executed and an interrupt is recognized prior to completion<br />
of the first iteration of the string operation, EFLAGS may be saved with RF=1 even<br />
though no data has been copied or stored. The Software Developer’s Manual states that<br />
RF will be set to 1 for such interrupt conditions only after the first iteration is complete.<br />
Implication: Software may not operate correctly if it relies on the value saved for EFLAGS.RF when<br />
an interrupt is recognized prior to the first iteration of a string instruction. Debug<br />
exceptions due to instruction breakpoints are delivered correctly despite this erratum;<br />
this is because the erratum occurs only after the processor has evaluated instructionbreakpoint conditions.<br />
Workaround: Software whose correctness depends on value saved for EFLAGS.RF by delivery of the<br />
affected interrupts can disable fast-string operation by clearing Fast-String Enable in bit<br />
0 in the IA32_MISC_ENABLE MSR (1A0H).<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV50. Accessing Physical Memory Space 0-640K through the Graphics<br />
Aperture May Cause Unpredictable System Behavior<br />
Problem: The physical memory space 0-640K when accessed through the graphics aperture may<br />
result in a failure for writes to complete or reads to return incorrect results.<br />
Implication: A hang or functional failure may occur during graphics operation such as OGL or OCL<br />
conformance tests, 2D/3D games and graphics intensive application.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV51. PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full<br />
Problem: The Software Developer’s Manual states that no PMI should be generated when PEBS<br />
index reaches PEBS Absolute Maximum. Due to this erratum, a PMI may be generated<br />
even though the PEBS buffer is full.<br />
Implication: PEBS may trigger a PMI even though the PEBS index has reached the PEBS Absolute<br />
Maximum.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 31<br />
BV52. Instructions Retired Event May Over Count Execution of IRET<br />
Instructions<br />
Problem: Under certain conditions, the performance monitoring event Instructions Retired (Event<br />
C0H, Unmask 00H) may over count the execution of IRET instruction.<br />
Implication: Due to this erratum, performance monitoring event Instructions Retired may over<br />
count.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV53. PCIe* Link May Unexpectedly Exit Loopback State<br />
Problem: The PCIe Port is capable of functioning as 3 independent PCIe controllers. Due to this<br />
erratum, if more than one of the controllers is in Loopback.Active state and configured<br />
as a loopback slave and if any one of these controllers transition to Loopback.Exit, all<br />
controllers in Loopback.Active will transition to Loopback.Exit.<br />
Implication: Loopback.Active state on a given Link may unexpectedly exit. Software should avoid<br />
configuring more than one of the PCIe Controllers as Loopback slave concurrently.<br />
Workaround: PCIe endpoints should avoid configuring more than one of PCIe Controllers as Loopback<br />
slave.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV54. The RDRAND Instruction Will Not Execute as Expected<br />
Problem: On processors that support the RDRAND instruction, that capability should be reported<br />
via the setting of CPUID.01H:ECX.RDRAND[bit 30]. Due to this erratum, that bit will<br />
not be set, and the execution of the RDRAND instruction will result in a #UD exception.<br />
Implication: Software will not be able to utilize the RDRAND instruction<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum to report RDRAND<br />
as present via CPUID and allow proper execution of RDRAND.<br />
Status: For the steppings affected, see the Summary Tables of Changes.32 Specification Update<br />
BV55. A PCIe* Device That Initially Transmits Minimal Posted Data Credits<br />
May Cause a System Hang<br />
Problem: Under certain conditions, if a PCIe device that initially transmits posted data credits<br />
less than Max_Payload_Size/16 + 4 (16B/4DW is unit of data flow control) and is the<br />
target of a Peer-to-Peer write of Max_Payload_Size, the system may hang due to<br />
Posted Data credit starvation.<br />
Implication: Under certain conditions, the processor may encounter a Posted Data credit starvation<br />
scenario and hang.<br />
Workaround: A BIOS code change has been identified and may be implemented as a workaround for<br />
this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV56. PCI Express* Gen3 Receiver Return Loss May Exceed Specifications<br />
Problem: The PCIe Base Specification includes a graph that sets requirements for maximum<br />
receiver return loss versus frequency. Due to this erratum, the receiver return loss for<br />
common mode and differential mode may exceed those requirements at certain<br />
frequencies. Under laboratory conditions, Intel has observed violations of as much as<br />
1 dB.<br />
Implication: The PCI Express Gen3 Base Specification for receiver return loss may be exceeded. No<br />
functional failures have been observed due to this erratum.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV57. Direct Access Via VT-d to The Processor Graphics Device May Lead to a<br />
System Hang<br />
Problem: Under a complex set of conditions, while using VT-d (Virtualization Technology for<br />
Directed I/O) with the processor graphics device, direct access to the virtualized<br />
processor graphics device can lead to a system hang or restart.<br />
Implication: Systems providing direct access to processor graphics device via VT-d may hang or<br />
restart. Intel has not observed this erratum with any commercially available system.<br />
Workaround: VMM’s should ensure that all processor graphics device interactions conform to<br />
guidance published in the Intel® Open Source HD Graphics Programmer's Reference<br />
Manual and driver writers guide.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 33<br />
BV58. An Event May Intervene Before a System Management Interrupt That<br />
Results from IN or INS<br />
Problem: If an I/O instruction (IN, INS, OUT, or OUTS) results in an SMI (system-management<br />
interrupt), the processor will set the IO_SMI bit at offset 7FA4H in SMRAM. This<br />
interrupt should be delivered immediately after execution of the I/O instruction so that<br />
the software handling the SMI can cause the I/O instruction to be re-executed. Due to<br />
this erratum, it is possible for another event (e.g., a nonmaskable interrupt) to be<br />
delivered before the SMI that follows the execution of an IN or INS instruction.<br />
Implication: If software handling an affected SMI uses I/O instruction restart, the handler for the<br />
intervening event will not be executed.<br />
Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was<br />
triggered by an instruction that read from an I/O port. The SMM handler must not<br />
restart an I/O instruction if the platform has not been configured to generate a<br />
synchronous SMI for the recorded I/O port address.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to<br />
L0 During Upconfiguration<br />
Problem: The processor should not associate any lanes that were not part of the initial link<br />
training in subsequent upconfiguration requests from an endpoint. Due to this erratum,<br />
the processor may associate any Lane that has exited Electrical Idle, even if it is<br />
beyond the width of the initial Link training.<br />
Implication: Upconfiguration requests may result in a Link wider than the initially-trained Link.<br />
Workaround: Endpoints must ensure that upconfiguration requests do not request a Link width wider<br />
than that negotiated during initial Link training.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV60. The Processor May Not Comply With PCIe* Equalization Preset<br />
Reflection Requirements for 8 GT/s Mode of Operation<br />
Problem: In endpoint-initiated transitions to Polling.Compliance at the 8 GT/s transfer rate, the<br />
processor must reflect, in its ordered sets, the Transmitter Preset requested by the<br />
endpoint regardless of preset legality. Due to this erratum, the processor will reflect<br />
the Transmitter Preset in use after an endpoint requests a reserved Transmitter Preset<br />
rather than the requested preset.<br />
Implication: Endpoints requiring reserved Transmitter Presets to be reflected may be adversely<br />
affected. Intel has not observed failures due to this erratum with any commercially<br />
available devices.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.34 Specification Update<br />
BV61. Processor May Issue PCIe* EIEOS at Incorrect Rate<br />
Problem: When initiating a Secondary Bus Reset or Link Disable procedure while a PCIe Link is in<br />
Recovery state, the processor should send an EIEOS (Electrical Idle Exit Ordered Set)<br />
after every 32 TS (Training Set) Ordered Sets. Due to this erratum, the processor may<br />
send an EIEOS after every 33 TS Ordered Sets.<br />
Implication: The processor may send an incorrect number of TS Ordered Sets between two EIEOS<br />
Ordered Sets when it initiates Secondary Bus Reset or Link Disable. Intel has not<br />
observed any failures with commercially available devices due to this erratum.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV62. Reduced Swing Output Mode Needs Zero De-emphasis to be<br />
Supported in PCIe* 5GT/s Speed<br />
Problem: It may not be possible to support the PCIe Transmitter Preset 1 and/or Transmitter<br />
Preset 0 equalization requests in Phase 0 or Phase 2 of Recovery.Equalization LTSSM<br />
states when operating in 8GT/s in reduced or half swing mode, if 0dB transmitter deemphasis needs to be supported when operating at 5GT/s.<br />
Implication: This erratum does not affect normal full swing mode of operation. Endpoints requiring<br />
0dB support in half-swing mode should avoid requesting Transmitter Preset 1 and/or<br />
Transmitter Preset 0 as preset requests in Phase 0 or Phase 2 of Recovery.Equalization<br />
when operating in 8GT/s.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV63. PCIe* Root-port Initiated Compliance State Transmitter Equalization<br />
Settings May be Incorrect<br />
Problem: If the processor is directed to enter PCIe Polling.Compliance at 5.0 GT/s or 8.0 GT/s<br />
transfer rates, it should use the Link Control 2 Compliance Preset/De-emphasis field<br />
(bits [15:12]) to determine the correct de-emphasis level. Due to this erratum, when<br />
the processor is directed to enter Polling.Compliance from 2.5 GT/s transfer rate, it<br />
retains 2.5 GT/s de-emphasis values.<br />
Implication: The processor may operate in Polling.Compliance mode with an incorrect transmitter<br />
de-emphasis level.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV64. PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s<br />
Problem: Due to this erratum, if a link partner transitions to RxL0s state within 20 ns of entering<br />
L0 state, the PCIe controller may incorrectly log an error in ?Correctable Error<br />
Status.Receiver Error Status? field (Bus 0, Device 2, Function 0, 1, 2 and Device 6,<br />
Function 0, offset 1D0H, bit 0).<br />
Implication: Correctable receiver errors may be incorrectly logged. Intel has not observed any<br />
functional impact due to this erratum with any commercially available add-in cards.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 35<br />
BV65. Reception of Certain Malformed Transactions May Cause PCIe* Port to<br />
Hang Rather Than Reporting an Error<br />
Problem: If the processor receives an upstream malformed non posted packet for which the type<br />
field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then<br />
due to this erratum the integrated PCIe controller may hang instead of reporting the<br />
malformed packet error or issuing an unsupported request completion transaction.<br />
Implication: Due to this erratum, the processor may hang without reporting errors when receiving a<br />
malformed PCIe transaction. Intel has not observed this erratum with any commercially<br />
available device.<br />
Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported<br />
requests with 4 DW header formats.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV66. PCIe* Link Width May Degrade After a Warm Reset<br />
Problem: PCIe link width may degrade after a warm reset if the Link is operating at 8.0 GT/s or<br />
5.0 GT/s transfer speeds prior to the reset.<br />
Implication: Due to this erratum, the PCIe link may retain to a narrower width, e.g. from x16 to x4.<br />
Workaround: A BIOS code change has been identified and may be implemented as a workaround for<br />
this erratum. .<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV67. MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate<br />
Problem: If the processor is in a package C-state for an extended period of time (greater<br />
than 40 seconds) with no wake events, the value in the<br />
MSR_PKG_C{2,3,6,7}_RESIDENCY MSRs (60DH and 3F8H–3FAH) will not be accurate.<br />
Implication: Utilities that report C-state residency times will report incorrect data in cases of long<br />
duration package C-states.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV68. PCIe* Link May Not Enter Loopback.Active When Directed<br />
Problem: When an endpoint directs the processor to enter loopback slave mode at 8 GT/s via TS1<br />
ordered sets with both the Loopback and Compliance Receive bits set, the PCIe link<br />
should directly enter Loopback.Active state. Due to this erratum, the processor must<br />
achieve block alignment on all looped back lanes prior to entering Loopback.Active.<br />
Implication: The processor will not enter Loopback.Active state as a loopback slave if any lane in a<br />
link cannot achieve block alignment.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.36 Specification Update<br />
BV69. Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value<br />
for VEX.vvvv May Produce a #NM Exception<br />
Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (InvalidOpcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to<br />
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-NotAvailable) exception.<br />
Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead<br />
of a #UD exception.<br />
Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of<br />
the VAESIMC and VAESKEYGENASSIST instructions.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV70. Unexpected #UD on VZEROALL/VZEROUPPER<br />
Problem: Execution of the VZEROALL or VZEROUPPER instructions in 64-bit mode with VEX.W set<br />
to 1 may erroneously cause a #UD (invalid-opcode exception).<br />
Implication: The affected instructions may produce unexpected invalid-opcode exceptions in 64-bit<br />
mode.<br />
Workaround: Compilers should encode VEX.W = 0 for the VZEROALL and VZEROUPPER instructions.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV71. PCIe* Root Port May Not Initiate Link Speed Change<br />
Problem: The PCIe Base specification requires the upstream component to maintain the PCIe link<br />
at the target link speed or the highest speed supported by both components on the<br />
link, whichever is lower. PCIe root port will not initiate the link speed change without<br />
being triggered by the software when the root port maximum link speed is configured<br />
to be 5.0 GT/s. System BIOS will trigger the link speed change under normal boot<br />
scenarios. However, BIOS is not involved in some scenarios such as link disable/reenable or secondary bus reset and therefore the speed change may not occur unless<br />
initiated by the downstream component. This erratum does not affect the ability of the<br />
downstream component to initiate a link speed change. All known 5.0Gb/s-capable<br />
PCIe downstream components have been observed to initiate the link speed change<br />
without relying on the root port to do so.<br />
Implication: Due to this erratum, the PCIe root port may not initiate a link speed change during<br />
some hardware scenarios causing the PCIe link to operate at a lower than expected<br />
speed. Intel has not observed this erratum with any commercially available platform.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 37<br />
BV72. Successive Fixed Counter Overflows May be Discarded<br />
Problem: Under specific internal conditions, when using Freeze PerfMon on PMI feature (bit 12 in<br />
IA32_DEBUGCTL.Freeze_PerfMon_on_PMI, MSR 1D9H), if two or more PerfMon Fixed<br />
Counters overflow very closely to each other, the overflow may be mishandled for some<br />
of them. This means that the counter’s overflow status bit (in<br />
MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally,<br />
PMI interrupt may be missed if software programs a counter in Sampling-Mode (PMI bit<br />
is set on counter configuration).<br />
Implication: Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is<br />
used.<br />
Workaround: Software can avoid this by:<br />
1. Avoid using Freeze PerfMon on PMI bit<br />
2. Enable only one fixed counter at a time when using Freeze PerfMon on PMI<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV73. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a<br />
#NM Exception<br />
Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (InvalidOpcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-notavailable) exception will be raised instead of #UD exception.<br />
Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on<br />
an FXSAVE or an FXRSTOR with a VEX prefix.<br />
Workaround: Software should not use FXSAVE or FXRSTOR with the VEX prefix.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV74. VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM<br />
Entry to the Shutdown State<br />
Problem: If VM entry is made with the "virtual NMIs" and "NMI-window exiting", VM-execution<br />
controls set to 1, and if there is no virtual-NMI blocking after VM entry, a VM exit with<br />
exit reason "NMI window" should occur immediately after VM entry unless the VM entry<br />
put the logical processor in the wait-for SIPI state. Due to this erratum, such VM exits<br />
do not occur if the VM entry put the processor in the shutdown state.<br />
Implication: A VMM may fail to deliver a virtual NMI to a virtual machine in the shutdown state.<br />
Workaround: Before performing a VM entry to the shutdown state, software should check whether<br />
the “virtual NMIs” and “NMI-window exiting” VM-execution controls are both 1. If they<br />
are, software should clear “NMI-window exiting” and inject an NMI as part of VM entry.<br />
Status: For the steppings affected, see the Summary Tables of Changes.38 Specification Update<br />
BV75. Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate<br />
Translations For 64-Bit Linear Addresses<br />
Problem: Executions of the INVVPID instruction outside 64-bit mode with the INVVPID type<br />
"individual-address invalidation" ignore bits 63:32 of the linear address in the INVVPID<br />
descriptor and invalidate translations for bits 31:0 of the linear address.<br />
Implication: The INVVPID instruction may fail to invalidate translations for linear addresses that set<br />
bits in the range 63:32. Because this erratum applies only to executions outside 64-bit<br />
mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to<br />
invalidate translations for a 64-bit guest. Intel has not observed this erratum with any<br />
commercially available software.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV76. PCIe* Controller May Not Properly Indicate Link Electrical Idle<br />
Condition<br />
Problem: The processor supports a x16 PCIe* port, which can be bifurcated into three<br />
independent links, enumerated as Bus 0, Device 1, Function 0-2. Due to this erratum,<br />
if the port is bifurcated and Function 1 or 2 is disabled, the PCIe controller may not<br />
properly indicate Link electrical idle condition to the Power Control Unit.<br />
Implication: An incorrect Link electrical idle indication may prevent the processor from entering the<br />
lowest power mode, which may cause higher power consumption on VccIO and VccSA.<br />
Intel has not observed any functional failure or performance impact due to this<br />
erratum.<br />
Workaround: If Bus 0, Device 1, Function 1 or 2 is disabled, do not configure the x16 port to allocate<br />
lanes to those functions.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV77. PCIe* Controller May Not Enter Loopback<br />
Problem: The PCIe controller is expected to enter loopback if any lane in the link receives two<br />
consecutive TS1 ordered sets with the Loopback bit set. Due to this erratum, if two<br />
consecutive TS1 ordered sets are received only on certain lanes, the controller may not<br />
enter loopback.<br />
Implication: Intel has not observed any functional issue with any commercially available PCIe<br />
devices.<br />
Workaround: None Identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV78. Link Margin Characterization May Hang Link<br />
Problem: The processor supports tools and mechanisms to characterize and measure margins for<br />
the PCIe interface. Due to this erratum, when performing link margin-to-failure<br />
characterization, it is possible that a high bit error rate may cause the link to hang.<br />
Implication: Under extreme conditions, poor link quality during link characterization may result in<br />
processor hang. Intel has not observed this erratum with any commercially available<br />
platforms under normal operating conditions.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
Specification Update 39<br />
BV79. Unused PCIe* Lanes May Report Correctable Errors<br />
Problem: Due to this erratum, during PCIe* link downconfiguration, unused lanes may report a<br />
Correctable Error Detected in Bus 0, Device 1, Function 0-2, and Device 6, Function 0,<br />
Offset 158H, Bit 0.<br />
Implication: Correctable Errors may be reported by a PCIe controller for unused lanes.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV80. RDMSR of IA32_PERFEVTSEL{4-7} May Return Erroneous Information<br />
Problem: When CPUID.0AH:EAX[15:8] reports 8 general-purpose performance monitoring<br />
counters per logical processor, RDMSR of IA32_PERFEVTSEL{4-7} (MSR 18AH-18DH)<br />
may not return the same value previously written by software.<br />
Implication: Software should not rely on values read from these MSRs.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV81. PCIe* Link May Fail Link Width Upconfiguration<br />
Problem: The processor supports PCIe Hardware Autonomous Width management, in which a<br />
PCIe link can autonomously vary its width. Due to this erratum, a link that performs a<br />
speed change while in a reduced width may no longer be able to return to a wider link<br />
width.<br />
Implication: PCIe links that perform speed changes while at a reduced link width may be limited to<br />
the link width in effect at the time of the speed change. Intel has not observed this<br />
erratum with any commercially available devices or platforms.<br />
Workaround: A BIOS code change has been identified and may be implemented as a workaround for<br />
this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV82. Graphics L3 Cache Parity Errors May Not be Detected<br />
Problem: The graphics engine should detect parity errors within the Graphics L3 cache. However,<br />
due to this erratum, graphics L3 cache parity errors may not be detected.<br />
Implication: There may be undetected parity errors from workloads submitted to the execution units<br />
of the graphics engine leading to unpredictable graphics system behavior.<br />
Workaround: It is possible for the graphics driver to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.40 Specification Update<br />
BV83. A PCIe* Link That is in Link Disable State May Prevent DDR I/O<br />
Buffers From Entering a Power Gated State<br />
Problem: When entering Link Disable LTSSM state, the PCIe controller may not properly indicate<br />
the Link electrical idle condition.<br />
Implication: An incorrect Link electrical idle indication may prevent the DDR I/O buffers from<br />
entering a power gated state, which may cause higher power consumption on VccIO<br />
and VccSA. Intel has not observed any functional failure or performance impact due to<br />
this erratum.<br />
Workaround: A BIOS code change has been identified and may be implemented as a workaround for<br />
this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes.<br />
BV84. REP MOVSB May Incorrectly Update ECX, ESI, and EDI<br />
Problem: Under certain conditions, if the execution of a REP MOVSB instruction is interrupted,<br />
the values of ECX, ESI and EDI may contain values that represent a later point in the<br />
execution of the instruction than the actual interruption point.<br />
Implication: Due to this erratum ECX, ESI, and EDI may be incorrectly advanced, resulting in<br />
unpredictable system behavior.<br />
Workaround: It is possible for the BIOS to contain a workaround for this erratum.<br />
Status: For the steppings affected, see the Summary Tables of Changes<br />
BV85. Performance-Counter Overflow Indication May Cause Undesired<br />
Behavior<br />
Problem: Under certain conditions (listed below) when a performance counter overflows, its<br />
overflow indication may remain set indefinitely. This erratum affects the generalpurpose performance counters IA32_PMC{0-7} and the fixed-function performance<br />
counters IA32_FIXED_CTR{0-2}. The erratum may occur if any of the following<br />
conditions are applied concurrent to when an actual counter overflow condition is<br />
reached:<br />
1. Software disables the counter either globally through the IA32_PERF_GLOBAL_CTRL<br />
MSR (38FH), or locally through the IA32_PERFEVTSEL{0-7} MSRs (186H-18DH), or the<br />
IA32_FIXED_CTR_CTRL MSR (38DH).<br />
2. Software sets the IA32_DEBUGCTL MSR (1D9H) FREEZE_PERFMON_ON_PMI bit<br />
[12].<br />
3. The processor attempts to disable the counters by updating the state of the<br />
IA32_PERF_GLOBAL_CTRL MSR (38FH) as part of transitions such as VM exit, VM entry,<br />
SMI, RSM, or processor C-state.<br />
Implication: Due to this erratum, the corresponding overflow status bit in<br />
IA32_PERF_GLOBAL_STATUS MSR (38DH) for an affected counter may not get cleared<br />
when expected. If a corresponding counter is configured to issue a PMI (performance<br />
monitor interrupt), multiple PMIs may be signaled from the same overflow condition.<br />
Likewise, if a corresponding counter is configured in PEBS mode (applies to only the<br />
general purpose counters), multiple PEBS events may be signaled.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes<br />
Specification Update 41<br />
BV86. RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result<br />
Problem: When CPUID.A.EAX[15:8] reports 8 general-purpose performance monitoring counters<br />
per logical processor, RDMSR of IA32_PERFEVTSEL4-7 (MSR 18AH:18DH) may not<br />
return the same value as previously written.<br />
Implication: Software should not rely on the value read from these MSRs. Writing these MSRs<br />
functions as expected.<br />
Workaround: None identified.<br />
Status: For the steppings affected, see the Summary Tables of Changes<br />
BV87. VEX.L is Not Ignored with VCVT*2SI Instructions<br />
Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and<br />
VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and<br />
will cause a #UD.<br />
Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI,<br />
VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions.<br />
Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.<br />
Status: For the steppings affected, see the Summary Tables of Changes<br />
§ §42 Specification Update<br />
Specification Changes<br />
The Specification Changes listed in this section apply to the following documents:<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic<br />
Architecture<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:<br />
Instruction Set Reference Manual A-M<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:<br />
Instruction Set Reference Manual N-Z<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:<br />
System Programming Guide<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:<br />
System Programming Guide<br />
There are no new Specification Changes in this Specification Update revision.<br />
§ §<br />
Specification Update 43<br />
Specification Clarifications<br />
The Specification Clarifications listed in this section may apply to the following<br />
documents:<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic<br />
Architecture<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:<br />
Instruction Set Reference Manual A-M<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:<br />
Instruction Set Reference Manual N-Z<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:<br />
System Programming Guide<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:<br />
System Programming Guide<br />
There are no new Specification Changes in this Specification Update revision.<br />
§ §44 Specification Update<br />
Documentation Changes<br />
The Documentation Changes listed in this section apply to the following documents:<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic<br />
Architecture<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:<br />
Instruction Set Reference Manual A-M<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:<br />
Instruction Set Reference Manual N-Z<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:<br />
System Programming Guide<br />
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:<br />
System Programming Guide<br />
All Documentation Changes will be incorporated into a future version of the appropriate<br />
Processor documentation.<br />
Note: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's<br />
Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel®<br />
64<br />
and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow<br />
the link below to become familiar with this file.<br />
http://developer.intel.com/products/processor/manuals/index.htm<br />
There are no new Documentation Changes in this Specification Update revision.<br />
§ §<br />
<br />
Credit : <a href="http://www.intel.com/content/www/us/en/processors/core/core-i7-processor.html">http://www.intel.com/content/www/us/en/processors/core/core-i7-processor.html</a>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-36503938961021343962011-10-02T10:58:00.000-07:002011-10-02T11:03:34.181-07:00WINDOWS 7 Professional SP1 Lite x64WINDOWS 7 Professional SP1 Lite x64<br /><br />Download : <a href="http://tinyurl.com/42kndpg">http://tinyurl.com/42kndpg</a><br /><br />Now that the <a href="http://www.intowindows.com/download-official-windows-7-and-windows-server-2008-r2-service-pack-1-release-candidate/" target="_blank">Service Pak 1 for Windows 7</a> is available for download, you might want slipstream it into the Windows 7 installation DVD. The slipstreamed DVD comes in handy as you won’t need to install the Service Pack every time after <a id="KonaLink0" class="kLink" style="text-decoration: underline ! important; position: static; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important;" href="#"><font style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;" color="#00aef0"><span class="kLink" style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;">Windows </span><span class="kLink" style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;">installation</span></font></a>.</p><br /><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/Windows7SP1.jpg"><img style="display: inline; border-width: 0px;" title="Windows 7 SP1" src="http://www.intowindows.com/wp-content/uploads/2010/11/Windows7SP1_thumb.jpg" alt="Windows 7 SP1" border="0" height="158" width="240"></a></p><br /><p style="text-align: justify;">Slipstreaming SP1 into the installation DVD or ISO can be done with the help of <a href="http://www.intowindows.com/5-free-tools-to-customize-tweak-windows-7-installation-setup/" target="_blank">Windows 7 installation configuring tools</a>. In this guide, we are using RT Seven Lite tool to integrate SP1 into Windows 7 installation DVD.</p><br /><p style="text-align: justify;"><br /></p><p style="text-align: justify;">By following this guide, you will be able to create bootable Windows 7 SP1 ISO file.</p><br /><p style="text-align: justify;"><br /></p><p style="text-align: justify;"><strong>Procedure:</strong></p><br /><p style="text-align: justify;"><strong>1</strong>. <a rel="nofollow" href="http://www.rt7lite.com/downloads.html" target="_blank">Download</a>, install and run RT Seven Lite tool. We recommend using RT Seven Lite v2.0 and above only.</p><br /><p style="text-align: justify;"><br /><br /></p><p style="text-align: justify;"><strong>2</strong>. Under the <strong>Home</strong> tab, click <strong>Browse</strong> button to browse to the Windows 7 installation ISO file or setup folder. If you select the ISO option, you will also need to specify a location to extract the ISO file. In this guide, we have selected ISO file option.</p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep1.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step1" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep1_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step1" border="0" height="356" width="582"></a></p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep2.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step2" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep2_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step2" border="0" height="174" width="487"></a></p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep23.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step23" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep23_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step23" border="0" height="356" width="583"></a></p><br /><p style="text-align: justify;"><strong>3</strong>. You will see the Extracting Image message. The process may take a while. Once the process is completed, you will be prompted to select your <a id="KonaLink1" class="kLink" style="text-decoration: underline ! important; position: static; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important;" href="#"><font style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;" color="#00aef0"><span class="kLink" style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;">Windows </span><span class="kLink" style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;">7 </span><span class="kLink" style="color: rgb(0, 174, 240) ! important; font-family: inherit ! important; font-weight: inherit ! important; font-size: inherit ! important; position: static;">edition</span></font></a>. Select your edition and also enable the option named <strong>Slipstream Service Pack</strong> before clicking the <strong>OK</strong> button.</p><br /><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep3.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step3" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7InstallationDVDStep3_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 Installation DVD Step3" border="0" height="359" width="428"></a></p><br /><p style="text-align: justify;"><br /></p><p style="text-align: justify;"><strong>4</strong>. <strong>RT Service Pack Slipstream</strong> box will be opened. Here, just input the Service Pack file for Windows 7 by clicking the <strong>Browse</strong> button on the left and navigating to the SP1 file. Click on the <strong>Start</strong> button.</p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISO.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISO_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO" border="0" height="406" width="551"></a></p><br /><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep11.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step11" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep11_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step11" border="0" height="406" width="551"></a></p><br /><p style="text-align: justify;"><strong>5</strong>. Wait for a few minutes until you see the Proceed button. Click on the <strong>Proceed</strong> button to start loading the image and other things. Once done, switch to <strong>Task</strong> tab.</p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep12.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step12" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep12_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step12" border="0" height="406" width="551"></a></p><br /><p style="text-align: justify;"><strong>6</strong>. Under the <strong>Task</strong> tab, select <strong>ISO Bootable</strong> option and then switch to <strong>ISO-Bootable</strong> tab.</p><br /><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep15.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step15" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep15_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step15" border="0" height="356" width="582"></a></p><br /><p style="text-align: justify;"><strong>7</strong>. Here, select <strong>Create Image</strong> option in Mode drop-down list. If you want to directly burn the files to a DVD, please select Direct Burn option in the Mode drop-down list. In this guide, we have selected Create Image option.</p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep16.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step16" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep16_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step16" border="0" height="357" width="584"></a></p><br /><p style="text-align: justify;"><strong>8</strong>. Click on the <strong>Make ISO</strong> button and choose a location to save your ISO file. Your Windows 7 SP1 ISO image should be ready in a while.</p><br /><p style="text-align: justify;"><a href="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep18.jpg"><img style="display: inline; border-width: 0px;" title="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step18" src="http://www.intowindows.com/wp-content/uploads/2010/11/SlipstreamWindows7SP1IntoWindows7DVDISOstep18_thumb.jpg" alt="Slipstream Windows 7 SP1 Into Windows 7 DVD ISO step18" border="0" height="361" width="589"></a></p><br /><p style="text-align: justify;"><strong>9</strong>. You are done! You can now delete the temporary folder that you have selected in step 2 to extract Windows ISO file. Good luck!</p><br /><br /><p style="text-align: justify;"><br /></p><p style="text-align: justify;">Also read <a href="http://www.intowindows.com/how-to-create-unattended-windows-7-installation-setup/" target="_blank">how to create unattended Windows 7 installation DVD</a>.</p>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-82279321687386412492007-09-14T12:17:00.000-07:002007-10-27T07:59:28.276-07:00A Purchase Guide to Budget Notebooks<h1><br /> A Purchase Guide to Budget Notebooks<br /></h1><br /><img class="postimg" src="http://community.massgo.com/style_images/1/folder_team_icons/ico_globe.gif" alt="http://community.massgo.com/style_images/1/folder_team_icons/ico_globe.gif">WindowBlinds 6.0<img class="postimg" src="http://community.massgo.com/style_images/1/folder_team_icons/ico_globe.gif" alt="http://community.massgo.com/style_images/1/folder_team_icons/ico_globe.gif"><br><br>WindowBlinds is a one-of-a-kind utility that allows Windows users to completely change the look and feel of the Windows interface by applying a new skin. There are thousands of different skins to choose from that are freely downloadable from the WindowBlinds website.<br><br>A WindowBlinds skin can make Windows look like an alternative operating system, like their favorite sports or car brand, or something completely new. Because WindowBlinds uses the latest hardware acceleration features of modern video cards, WindowBlinds won't slow down your computer and uses very little memory.<br><br>WindowBlinds is safe and easy to use. It doesn't alter any system files and users can switch between the default Windows look and feel and a custom WindowBlinds skin with the click of a button. In addition, WindowBlinds has been tested to ensure it works with Windows Vista, so you know it is compatible, reliable,, and more secure. <br><br><a href="http://storage.stardock.com/files/WindowBlinds6_public.exe">Download It Now!!</a><br /><p><br /> Since it became commercially available back in the early eighties, notebooks called the attention of computer users because of its small size and portability. Not much of a commercial success back then, it only took a short time before the computer industry improved this item, up to a point that is now considered to be one of the best selling computer consumer products.<br><br>For one who intends to buy a budget notebook, he may have some difficulties in picking the right one, since there are several notebook manufactures offering so many models. Budget notebooks are in a class by itself with basic features but capable of delivering full solutions for computer related tasks.<br><br>For an easy guide to budget notebooks, check the following major manufactures:<br><br>SONY<br><br>Sony VAIO notebooks are fashioned products targeted to consumers who demand flexibility and power without compromise. It is expected to find features such as 15.4`` WXGA, duo core processor and 100 gb hard disk. Although not the cheapest of budget notebooks, it compensates the higher price by offering more technological features.<br><br>Most common features one can expect from Sony budget notebooks: 1 - Intel Core Duo Processor T2250 1.72 Ghz; 2 - Windows Vista; 3 - 1 gb DDR2 ram; 4 - Widescreen XGA display type; 5 - Intel graphics media accelerator 950; 6 - 100 gb SATA hard disk 5400 rpm; 7 - CD-RW/DVD rom; 8 - wireless lan 802.11 a/b/g; 9 - Modem and Lan port 10/100; 10 - USB connectivity; 11 - It weighs around 6.5 pounds; 12 - Lithium ion battery up to 5.5 hours; 13 - One year limited warranty. Price starts from U$ 929.00 and up according with optional accessories.<br><br>DELL<br><br>With features such as 15.4`` WXGA, duo core processor and ATI Radeon Xpress graphics, Dell budget notebooks offer a flexible combination of power, mobile productivity and entertainment at a good price.<br><br>Most common features one can expect out of these notebooks are: 1 - AMD Turion 62 X2 1.8 ghz/1mb cache processor; 2 - Windows Vista; 3 - 512 mb ram; 4 - Widescreen XGA display type; 5 - ATI Radeon Xpress 256 mb video graphics chipset; 6 - Up to 80 gb hard disk; 7 - CD-RW/DVD rom; 8 - It weighs around 6 pounds; 9 - 9-cell lithium ion battery; 10 - One year limited warranty. Price starts from U$ 549.00 and up according with optional accessories.<br><br>TOSHIBA<br><br>All Toshiba budget notebooks feature an 15.4`` diagonal WXGA display, DVD optical drive which reads and writes up to 11 formats, high speed wireless lan (802.11 b/g) for easy connection in networks. <br><br>Most common features one can expect out of these notebooks are: 1 - Intel Celeron processor with 1+ Ghz; 2 - Windows Vista; 3 - 512 mb ram; 4 - Widescreen XGA display type; 5 - Radeon Xpress 200M video graphics chipset; 6 - 60 gb hard disk; 7 - CD-RW/DVD rom; 8 - wireless lan but no Bluetooth connectivity; 9 - Modem and Lan port 10/100 mbps; 10 - USB and firewire connectivity; 11 - It weighs around 5 pounds; 12 - 4-cell lithium ion battery; 13 - Tv-out s-video; 14 - One year parts and labor warranty. Price starts from U$ 599.00 and up according with optional accessories.<br><br>HP<br><br>HP Budget notebooks with features such as 15.4`` display screen, AMD Sempron 3500+ and a sophisticated black resin finish, offer an attractive mix of style, mobility and performance.<br><br>Expected features one can find in this HP notebook category: 1 - AMD Sempron 3500+; 2 - Windows Vista; 3 - 15.4`` WXGA Widescreen; 3 - 512 mb ddr2; 4 - CD-RW/DVD rom; 4 - Wireless connectivity 802.11b/g wlan; 5 - It weighs around 7 pounds; 6 - Nvidia video graphics chipset with 256 mb; 7 - 6-cell lithium ion battery; 8 - USB, lan and modem port; 9 - Integrated stereo speakers; 10 - 60 gb SATA hard disk; 11 - Tv-out s-video; 12 - One year warranty in parts and labor. Price starts from U$ 569.00 and up according with optional accessories.<br><br>A while ago portable electronics devices were a luxury at an expensive price. Nowadays it became an affordable must have kind of product for lots of people. Notebooks are in this category for sure! And basic notebooks are the best option for those who are in a tight budget. So, if portability is a must for your personal or professional computer related tasks, waste no more time. Get yourself a budget notebook!<br><br>Roberto Sedycias<br>IT Consultant for PoloMercantil<br><br>This article is under GNU FDL license and can be distributed without any previous authorization from the author. However the author´s name and all the URL´s (links) mentioned in the article and biography must be kept.<br /><br /></p><br /><hr><br /><p><br /><strong>About the Author:</strong> This article can also be accessed in portuguese language from the News Article section of page <a href="http://www.polomercantil.com.br/notebook.php">PoloMercantil</a><br><br>Roberto Sedycias has a bachelor degree in Business Administration and over 20 years experience in systems analysis and computer programming. Currently working as IT consultant for <a href="http://www.polomercantil.com.br">www.PoloMercantil.com.br</a>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-63823741867313710372007-09-08T05:01:00.000-07:002007-09-08T05:02:03.136-07:00Mac OS X Server version 10.4 Tiger offers 200+ new features<p class="intro">The fifth major release of Apple’s award-winning server operating system, Mac OS X Server version 10.4 Tiger offers 200+ new features and builds on more than 100 of the latest open source projects. Get started now with the 10-client edition for only $499. Or provide services to everyone on your network with the unlimited-client edition for $999.</p><br /> <img src="http://images.apple.com/server/macosx/images/indexadminscreens20050412.jpg" alt="Manage Macintosh and Windows workgroups" class="across" border="0" height="260" width="445"><br /> <p>Mac OS X Server gives you everything you need to provide standards-based workgroup and Internet services — without the complexity of Linux or the cost inherent in other UNIX-based solutions. Manage Mac and Windows <a href="/server/macosx/workgroupmanagement.html">workgroups</a>. Enable secure and efficient <a href="/server/macosx/collaborationservices.html">collaboration</a>. Host dynamic websites, stream media and run enterprise applications. And while you’re doing it — integrate seamlessly with your existing infrastructure. Best of all, Apple streamlines these management tasks with applications and utilities that are both powerful and easy to use.</p><br /> <img src="http://images.apple.com/server/macosx/images/indexunix20050429.gif" alt="UNIX-based" class="left" border="0" height="71" width="124"><br /> <h3>UNIX at the core</h3><br /><br /> <p>The power and simplicity of Mac OS X Server begin with a UNIX-based foundation built around the <a href="/server/macosx/">Mach microkernel</a> and the latest advances from the open source BSD community. The result is a stable, high-performance 64-bit computing platform that’s ideal for deploying server-based applications and services.</p><br /> <img src="http://images.apple.com/server/macosx/images/indexopensign20050429.gif" alt="Come in it's open" class="right" border="0" height="65" width="90"><br /> <h3>Open Standards. Apple Ease of Use.</h3><br /> <p>Instead of developing proprietary technologies, Apple has embraced the best open source projects, such as <a href="/server/macosx/webhosting.html">Apache</a>, <a href="/server/macosx/fileprint.html">Samba</a>, <a href="/server/macosx/opendirectory.html">OpenLDAP</a>, <a href="/server/macosx/opendirectory.html">Kerberos</a>, <a href="/server/macosx/mailservices.html">Postfix</a>, <a href="/server/macosx/collaborationservices.html">Jabber</a> and <a href="/server/macosx/mailservices.html">SpamAssassin</a>. Mac OS X Server integrates these robust technologies and enhances them with a unified, consistent management interface. Powerful administrative tools permit novices to configure and maintain core network services — while providing the advanced features you require if you’re an experienced IT professional.</p><br /><br /> <img src="http://images.apple.com/server/macosx/images/indexaclpermissons20050412.jpg" alt="ACL Permissions window" class="left" border="0" height="153" width="115"><br /> <h3>Model Citizen in a Multiplatform World</h3><br /> <p>Because it’s built on open standards, Mac OS X Server is compatible with your existing computing infrastructure. It uses native protocols to deliver directory services, <a href="/server/macosx/fileprint.html">file and printer sharing</a> and secure network access to Mac, <a href="/server/macosx/windowsservices.html">Windows</a> and Linux clients. New support for access control lists (ACLs) provides flexible file system permissions that are fully compatible with the native file permissions of Windows 2003 and Windows XP. And a standards-based directory services architecture called <a href="/server/macosx/opendirectory.html">Open Directory</a> offers centralized management of network resources using any LDAP server — even proprietary servers such as Microsoft Active Directory.</p><br /><br /> <img src="http://images.apple.com/server/macosx/images/indexiconserveradmin20050429.jpg" alt="Server Admin" class="right" border="0" height="64" width="64"><br /> <img src="http://images.apple.com/server/macosx/images/indexiconworkgroupmanager20050429.jpg" alt="Workgroup Manager" class="right" border="0" height="64" width="64"><br /> <h3>Industry-Leading Management Tools</h3><br /> <p>You don’t need to be a UNIX guru to take advantage of Mac OS X Server and its full complement of services. Server Admin provides a graphical user interface that makes it easy to configure, manage and monitor services from any Internet-connected Mac OS X system. You also get the powerful <a href="/server/macosx/workgroupmanagement.html">Workgroup Manager</a> application, an easy-to-use tool for setting up user accounts, defining groups and managing computing resources in a directory-based network environment.</p><br /> <h3>Fits into IT Budgets Everywhere</h3><br /> <p>Stable, compatible, easy to use and easy on the budget too. A complete suite of workgroup and Internet services is included in the box, so you can get started right away. Mac OS X Server is available in 10-client and unlimited-client editions. With the unlimited-client edition, there are no additional per-seat fees for connecting more users, making it an affordable solution for organizations of any size.</p>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-51959226635658990192007-09-08T04:57:00.000-07:002007-09-08T04:59:07.715-07:00Mac miniLive the digital life in stylish simplicity — up to 39% faster.<sup>1</sup> Just 6.5 inches square and 2 inches small, Mac mini lets you have more fun with your music, photos, and movies, more quickly and more easily. Enjoy them up close or far away with the included Apple Remote. The most affordable way to Intel Core 2 Duo, iLife ’08, and Front Row starts at $599.</p><br /><br /> <a href="intel.html"><img src="http://images.apple.com/macmini/images/index_intelcore2duo20070807.jpg" alt="Intel Core 2 Duo chip" class="left" border="0" height="126" width="124"></a><br /> <h3>Power has never been this economical.</h3><br /> <p style="margin-left: 150px;">Mac mini makes it easy and affordable to work with digital photos, movies, music, and the web. And now it all happens with the blazing speed of the <a href="intel.html">Intel Core 2 Duo.</a> Delivering unprecedented power in such a small package, the Mac mini runs up to 39% faster than previously. Coupled with the world’s most advanced operating system, Mac OS X, Mac mini runs all your modern and innovative software, speedily.</p><br /><br /> <a href="ilife.html"><img src="http://images.apple.com/macmini/images/index_ilife20070807.jpg" alt="iLife ’08" class="right" border="0" height="158" width="165"></a><br /> <h3>Your digital life starts here.</h3><br /> <p>Mac mini comes with <a href="ilife.html">iLife ’08</a>, a suite of easy-to-use applications that make it easy to make amazing things. Enhance, organize, and share your photos via iPhoto. Create calendars, books, and cards. Make an epic starring your kids in iMovie. Turn your photo and movie creations into professional DVDs with iDVD. Create original music in GarageBand, even if you can’t carry a tune. Make podcasts and blogs. Then publish them online via .Mac and iWeb.<sup>2</sup> You’ll be amazed at how quickly, easily, and beautifully you can share your digital life.</p><br /><br /> <a href="frontrow.html"><img src="http://images.apple.com/macmini/images/index_frontrow20070807.jpg" alt="Front Row" class="left" border="0" height="140" width="224"></a><br /><br /> <h3>Now showing.</h3><br /> <p>The full-screen <a href="frontrow.html">Front Row</a> media experience — with its intuitive menus, large text, and brilliant graphics — lets you browse the music, photos, and videos on your Mac mini as easily as you browse music on your iPod. The included Apple Remote lets you enjoy your media from anywhere in the room, from your desk chair to favorite sofa. Front Row and Mac mini can even play music, photos, and videos saved on other computers in the house, thanks to Bonjour instant networking.<sup>3</sup> So gather your friends and dazzle them with a slideshow of your vacation pics, a home movie, your latest playlist, or a DVD.</p><br /><br /> <a href="design.html"><img src="http://images.apple.com/macmini/images/design_dimensions20060228.jpg" alt="Mac mini Dimensions" class="right" border="0" height="101" width="208"></a><br /><br /> <h3>More Mac per square inch.</h3><br /> <p>Inside its petite 2-inch-tall, 6.5-inch-square anodized aluminum enclosure, Mac mini houses the fast Intel Core 2 Duo processor, an 80GB or 120GB hard drive, a slot-loading Combo drive or SuperDrive, as well as built-in wireless — all whisper-quiet. This modular <a href="design.html">design</a> lets you upgrade your current system to the elegance, simplicity, and reliability of Macintosh without a lot of extra expense. <a href="accessories.html">BYODKM</a>: Bring your own display, keyboard, and mouse (or buy new ones). Either way you’ll be up and running in minutes. </p><br /> <a href="specs.html"><img src="http://images.apple.com/macmini/images/index_ports20060229.jpg" alt="Mac mini ports" class="across" border="0" height="220" width="570"></a><br /> <p>Mac mini also gives you plenty of room to grow. Simply connect your digital devices, such as cameras, iPod, printer, camcorder, or keyboard, to the Mac mini over USB 2.0 or FireWire. Share files around your house at blazing speeds with built-in 10/100/1000BASE-T Ethernet. Enjoy high-quality sound on almost any speaker system with double-duty analog/digital audio. Record digital and analog sources through audio line in, perfect for your latest podcast in GarageBand. Mac mini gives you the built-in amenities you need to enjoy the digital lifestyle.</p><br /><br /> <br /> <li>Performance based on common application tasks in iPhoto ’08. Testing conducted by Apple in July 2007 using preproduction Mac mini units with 2.0GHz Intel Core 2 Duo; all other systems were production units. Safari HTML Load Speed (cached) test, Java Script, and Java VM are a subset of the i-Bench 5.0 benchmark. Performance tests are conducted using specific computer systems and reflect the approximate performance of Mac mini.</li><br /> <li>Some features require .Mac. The .Mac service is available to persons age 13 and older. Annual membership fee and Internet access required. Terms and conditions apply.</li> <br /> <li>Sharing photos requires a Mac with iPhoto. Sharing music and videos requires iTunes 6.0.4 or later.</li><br /> <li>Some options must be installed by Apple at the factory; the rest can be added in-store at an <a href="/retail/">Apple Retail Store</a> or an Apple authorized <a href="http://wheretobuy.apple.com/locator/">reseller</a>.</li>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-7686839199253646322007-09-05T10:35:00.000-07:002007-09-14T23:55:58.940-07:00Multi-Core Confrontation: Core 2 Quad Q6600 vs. Core 2 Duo E6850<h3 style="font-size: 18px;">Multi-Core Confrontation: Core 2 Quad Q6600 vs. Core 2 Duo E6850</h3><br /><br /><br /> <p class="date">Category: <a href="http://www.blogger.com/articles/cpu/">CPU</a></p><br /> <p class="date">by <a href="mailto:gavric@xbitlabs.com">Ilya Gavrichenkov</a> </p><br /> <p class="date">[ <strong>08/31/2007</strong> | 12:01 PM ]</p><br /><br /> <p class="description">While AMD keeps postponing the launch of their quad-core processors to the end of this year – beginning of next, Intel Company is offering very affordable quad-core CPUs from Core 2 Quad family. However, can Core 2 Quad processors be regarded as a worthy alternative to popular dual-core solutions?</p><br /><br /><br /><h4>Table of contents:</h4><br /> <ul><br /><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_2.html#sect0">Core 2 Quad Q6600 vs. Core 2 Duo E6850: General Information</a><br /></li><br /><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_3.html#sect0">Testbed and Methods</a><br /></li><br /><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_4.html#sect0">Overclocking</a><br /></li><br /><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_6.html#sect0">Performance</a><br /></li><br /><br /><ul><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_6.html#sect1">PCMark05</a><br /></li><br /><br /></ul><br /><br /><br /><ul><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_7.html#sect0">SYSmark 2007</a><br /></li><br /><br /></ul><br /><br /><br /><ul><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_8.html#sect0">3D Games</a><br /></li><br /><br /></ul><br /><br /><br /><ul><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_9.html#sect0">Audio and Video Encoding</a><br /></li><br /><br /></ul><br /><br /><br /><ul><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_10.html#sect0">Rendering</a><br /></li><br /><br /></ul><br /><br /><br /><ul><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_11.html#sect0">Other Applications</a><br /></li><br /><br /></ul><br /><br /><br /><li><a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_12.html#sect0">Conclusion</a><br /></li><br /><br /><br /></ul><br /><br /><br /><br /><br /> <div class="block" style="margin: 0px; padding: 0px;"><br /><p class="date"><b>Real-time Pricing and Availability:</b></p><br /><p class="date"><a>Intel Core?2 Quad Q6600, 2.40 GHz (BX80562Q6600) Boxed Processor Products </a></p><br /><table style="border: medium none ;" cellpadding="5"><tbody><tr><td style="border: medium none ;"><br /> <ul class="right-cat"><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&code=93&aon=%5E31&crawler_id=812029&dealId=VsFIYinLcibMXlFHFSnBhg%3D%3D&prjID=ds&url=http%3A%2F%2Fclickfrom.buy.com%2Fdefault.asp%3Fadid%3D15891%26sURL%3Dhttp%253A%252F%252Fwww.buy.com%252Fretail%252Fproduct.asp%253Fsku%253D203829458%2526SearchEngine%253DDealTime%2526SearchTerm%253D203829458%2526Type%253DPE%2526Category%253DComp%2526Gad%253D0&DealName=Intel%20Core%202%20Quad%20Q6600%202.40GHz%20Processor%20-%202.40GHz%20-%201066MHz%20FSB%20-%208MB%20L2%20...&MerchantID=9021&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=1&RR=1&NG=12&GR=1&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=281.00">Buy.com</a> - $281.00</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=394&aon=%5E&crawler_id=812104&dealId=lUDNAoOTBX5wodIf8ZBV9g%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.mwave.com%2Fmwave%2Fskuinc.hmx%3Fpromo%3DDM%26SKU%3DBA23383&amp;DealName=INTEL%20CORE%202%20QUAD%20Q6600%20%28BX80562Q6600%29%202.4GHZ%20EM64T%20QUAD%20CORE%20W%2F4MB%20X%202%20CAC...&MerchantID=9460&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&frameId=0&AR=3&RR=1&NG=12&GR=3&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=286.00">Mwave.com</a> - $279.00</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=238&aon=%5E162&crawler_id=812077&dealId=2LbHZAAg1I4Ok0aqI7dmsA%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.newegg.com%2FProduct%2FProduct.asp%3FItem%3DN82E16819115017%26ATT%3D19-115-017%26CMP%3DOTC-d3alt1me%26cm_mmc%3DOTC-d3alt1me-_-Processors-_-intel-_-19115017&amp;DealName=CPU%20INTEL%7CC2Q%20Q6600%202.40G%20775%208M%20R&MerchantID=300168&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&frameId=0&AR=5&RR=1&NG=12&GR=5&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=284.99">Newegg.com</a> - $284.99</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=12&aon=%5E&crawler_id=811105&dealId=7yDEOiAhtN5x1omUlIYATw%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.pcrush.com%2Fclickthru.asp%3Frefid%3D1135%26bp%3Dhttp%253A%252F%252Fwww%252Epcrush%252Ecom%252Fprodspec%252Easp%253Fln%253D1%2526itemno%253D89022&DealName=Core%202%20Quad%20Q6600%20%2F%202.4%20GHz%20Processor&MerchantID=9074&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=7&RR=1&NG=12&GR=7&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=312.49">pcRUSH.com</a> - $302.25</li><br /><br /></ul><br /></td><td style="border: medium none ;"><br /> <ul class="right-cat"><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&code=65&aon=%5E&crawler_id=811890&dealId=YaTYy40-NCAvEMr3arnVQQ%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.tigerdirect.com%2Fapplications%2Fsearchtools%2Fitem-details.asp%3FEdpNo%3D2905631%26Sku%3DCP1-DUO-Q6600%26SRCCODE%3DSHOPPINGDF%26CMP%3DOTC-SHOPPING&DealName=Intel%20Core%202%20Quad%20Q6600%20Processor%20-%202.40GHz%2C%208MB%20Cache%2C%201066MHz%20FSB%2C%20Kentsf...&MerchantID=90006&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=2&RR=1&NG=12&GR=2&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=588.48">TigerDirect.com</a> - $569.99</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=425&aon=%5E&crawler_id=810698&dealId=4OSjbTa9Y_b-GIBu6ePNsg%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.zipzoomfly.com%2Fjsp%2FProductDetail.jsp%3FProductCode%3D80864%26prodlist%3Dshopping&DealName=Intel%20Core%202%20Quad%20Q6600%20Quad-Core%20Processor%202.4GHz%2C%201066FSB%2C%20LGA775%2C%208MB%20ca...&MerchantID=9495&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=4&RR=1&NG=12&GR=4&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=279.90">ZipZoomfly.com</a> - $279.90</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=409&aon=%5E&crawler_id=810640&dealId=PQCjqh7mBirgBOlRzSy84w%3D%3D&prjID=ds&url=http%3A%2F%2Fwww.futurepowerpc.com%2Fscripts%2Fdetails.asp%3FPRDCODE%3DCPIN-RQ6600%26REFID%3DSC&DealName=Intel%20Core%202%20Quad%20Q6600%202.4Ghz%2F1066FSB%208M%20L2%20Processor&MerchantID=302479&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=6&RR=1&NG=12&GR=6&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=294.00">FuturePowerPC</a> - $294.00</li><br /><br /><li><a href="http://stat.dealtime.com/DealFrame/DealFrame.cmp?BEFID=1719&amp;code=1017&aon=%5E949&crawler_id=439959&dealId=Aquy-2ZqQRMVjeMOt1PChA%3D%3D&prjID=ds&url=http%3A%2F%2Fad.doubleclick.net%2Fclk%3B123793010%3B18358257%3Be%3Fhttp%3A%2F%2Flt.dell.com%2Flt%2Flt.aspx%3FCID%3D23853%26LID%3D549670%26DGC%3DBA%26DGSeg%3DDHS%26DURL%3Dhttp%3A%2F%2Faccessories.us.dell.com%2Fsna%2Fproductdetail.aspx%3Fsku%3DA0982831%2526cs%3D19%2526c%3Dus%2526l%3Den&DealName=Core2%20Q6600%202.4%20GHz%20Quad-Core%20Processor&MerchantID=439959&category=77&MT=nyc-pmt5-1&DB=sdcprod&MN=SE_SVC10&HasLink=yes&amp;frameId=0&AR=8&RR=1&NG=12&GR=8&ND=1&FPT=DSP&NDS=12&NMS=12&NDP=12&MRS=12&amp;CT=6&linkin_id=7000875&DMT=7&VK=7000875&searchID=5b0ad88bfe83fe9ed2a341d9&PD=38880473&dlprc=309.00">Dell</a> - $309.00</li><br /><br /></ul><br /></td></tr></tbody></table><br /></div><br /><br /><br /><br /> <div class="pager"><br /> <div class="bg"><div class="bg-l"><div class="bg-r"><br /> <strong>Pages : </strong><b>1</b> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_2.html">2</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_3.html">3</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_4.html">4</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_5.html">5</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_6.html">6</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_7.html">7</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_8.html">8</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_9.html">9</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_10.html">10</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_11.html">11</a> | <a href="http://www.blogger.com/articles/cpu/display/core2quad-q6600_12.html">12</a><br /><br /> </div></div></div><br /> </div><br /> <br /> <br /><br /><p>The Intel processor price cut that occurred a month ago turned into an important milestone on the multi-core processors’ way to user computer systems. The price of quad-core processors has finally dropped down to the level of dual-core solutions. To be more exact, the youngest model in the official Core 2 Quad lineup is priced exactly the same as the top Core 2 Duo CPU. This price, by the way, is set at $266, which seems quite sufficient to make processors with four computational cores much more popular than they used to be before.This particular situation inspired us to undertake another analytical investigation where we decided to arrange a duel between dual-core and quad-core processors priced identically. I am talking about Core 2 Duo E6850 and Core 2 Quad Q6600. True, a lot of users found themselves facing this difficult choice, as the above mentioned processor models are currently sold in retail stores at comparable prices. However, these processors are so different in their specifications that even true professionals cannot always make the most optimal choice between them with all certainty. These processors feature not only different number of computational cores, they also work at very different clock speeds and support busses running with different frequencies.</p><p>There is an opinion that a lot of resource-hungry applications that have be released or updated recently, can take real advantage of multi-core processor capabilities. At the same time, this is not always true about the older applications and games, the majority of which are still working with only one of two computational threads. Therefore, we decided to perform a special test session that will make a lot of things clear and help us decide if quad-core processors can really replace high-speed dual-core CPUs in different applications.</p><p>It is also very interesting to see the outcome of Core 2 Duo E6850 and Core 2 Quad Q6600 rivalry because both these processors use absolutely identical semiconductor dies. The thing is that contemporary quad-core Intel processors consist of a pair of dual-core dies mounted within the same LGA775 package. That is why we can actually expect dual- and quad-core processors from the Core family to demonstrate similar overclockability. This, at the same time, dives us some hope for Core 2 Quad Q6600 to overclock to the top frequencies that can be achieved with Core 2 Duo E6850. In other words, it should be even more exciting to compare Core 2 Duo E6850 and Core 2 Quad Q6600 from the overclocking standpoint than in the nominal operational mode. Moreover, both, Core 2 Duo E6850 as well as the recently released Core 2 Quad Q6600 are based on the new G0 core stepping, that boasts slightly better overclocking potential, according to <a href="http://www.blogger.com/articles/cpu/display/core2duo-e6850_11.html" target="_blank">our previously conducted research</a>.</p>Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-7169768501563808107.post-56854090787799615042007-06-24T21:06:00.000-07:002008-11-06T18:46:37.633-08:00Intel 8-core Xeon X5365 V8 Performance Preview<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggjzUgXFMRhKMZPVf1-YUr6PsvzK4ZV-A9Q25ANwhLRCeAjfr-uJGvJXohkSLK8R0nzvBQX6y90pKsettt93A5Ine9kx7Iy-hWhVIFNDemboDX7uFTyFfU6WAmME2VBIYhLc_XGngRMtUa/s1600-h/header.jpg"><img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggjzUgXFMRhKMZPVf1-YUr6PsvzK4ZV-A9Q25ANwhLRCeAjfr-uJGvJXohkSLK8R0nzvBQX6y90pKsettt93A5Ine9kx7Iy-hWhVIFNDemboDX7uFTyFfU6WAmME2VBIYhLc_XGngRMtUa/s320/header.jpg" alt="" id="BLOGGER_PHOTO_ID_5079478580667182370" border="0" /></a><br /><br /><a href="http://rapidshare.com/files/37402963/70.themes.for.Xp.With.installation.pack.rar">download 70 Theme Vista For XP NOW</a><br />Password: <a href="http://www.the-sourcewz.org/">www.the-sourcewz.org</a><br /><br /><a href="http://www.uploadtoday.com/download/?e48dac61e9dd8b4e16b98582e310c553"> Download screen sever freefire Now</a><br /><br />The demands of enthusiasts are ever growing and the relative success of Intel’s Quad Core Platform would certainly verify this. Intel however are taking a bold step and are attempting to position their new Quad Core Xeon processors towards the high end enthusiast sector. This is not only in direct competition to AMD’s Quad FX release but to further meet the demands of a high end multitasking environment.<br /><br />Today we are going to look at a pair of the new Quad Xeon X5365 processors running at 3.0ghz on a i5000X chipset.<br /><br />Multi Core/Multi CPU<br /><br />It wasn’t so long ago that even dual core was beyond the realities of many people, however today, multiple cores are firmly routed in the mainstream enthusiast market. The benefits of multicore are wide reaching, we can all enjoy faster response times and a more enjoyable multitasking environment. Even current consoles such as the Xbox 360 and Playstation 3 use multicore technology to power their gaming experience.<br /><br />The evolution of CPU development is such that, once dual core hit the masses, Intel already had released Quad Core processors for those with deeper pockets and higher demands. With multiple processors on Quad core architecture, it is clear to see where we are headed with all of this. How about future gaming titles with two cores handling the artificial intelligence, while other cores are left to deal with the everyday tasks?<br /><br />AMD were the first to bring multiple CPU/Core to the public with their Quad FX platform, however the performance was sadly lacking and it was a rather poor implementation when compared with the single die Intel Quad. AMD stated that the dual socket desktop market had a strong future and they would continue evolving after the quad core processors on K10 were released.<br /><br />However it is Intel who today have kindly supplied the (pre)review product on our bench. It can be traced back to the first demonstration at CES 2007 where it was codenamed V8. The particular setup we are looking at is an eight core desktop PC for media content creation.<br /><br />“Combining Quad Core processing and the advantages of Intel Core Microarchitecture, a media creation PC with dual Quad Core Xeon Processors is ideal for processor intensive, digital media usage models – speeding tasks like video encoding and transcoding. 3D Animation rendering, music editing and more. Eight processing cores also take advantage of today’s operating systems improved workload scheduling when running multiple applications simultaneously. It’s multitasking capability makes this platform a great choice for developers and media enthusiasts who can compile code or encode video in the background while working on other tasks”.<br />Up Close with V8<br /><br />Intel’s multi cpu solution is a much simpler proposition when compared with the Quad FX platform, the V8 platform is physically nothing more than a traditional workstation system based on quad core Xeon Clowertown processors installed into a i5000X Greencreek chipset. While this is hardly revoluntary, it is a stable and tried solution and as many of our readers will already be aware, Apple have been offering similar configurations with their latest high end “Mac Pro” range.<br /><br /><br />The Clowertown CPUs are based on Core micro-architecture and feature a quad core structure, which makes these very similar to the Kentsfield Core 2 Quad processors. We all know that Xeon processors are marketed towards server and high end workstation applications so the socket design remains slightly different from that we are used to seeing, they are LGA-771. Additionally a Xeon cpu differentiates from a standard Quad Cpu in that they can also work in a dual socket motherboard, which will require a special chipset.<br /><br />So it is clear so far that the Xeon's are being used due to the multi processor compatibility, however these processors are still faster than the desktop quad core equivalents (at 3.0ghz). The high end X5365 Clowertown models we will be using in this review also run on a 1333fsb which won’t be hitting standard desktop systems for a few months.<br /><br />Each Quad Core Xeon is split up into two dual core dies and each of these features a shared 4MB L2 cache for both cores. Therefore, each Quad Core Xeon has two L2 caches with a total of 8MB per CPU.<br /><br />For those of you who never read the diagrams, Intel is strongly promoting the economical aspects of these CPUs. The use of components with smaller die sizes increases the production yields by 20% and reduces the production cost by 12%.<br /><br />Xeon Specifications:<br />Clock Frequency: 3.0ghz<br />Bus Frequency: 1333mhz<br />TDP: 150w<br />Brand ID: Intel Xeon Processor<br />Processor Number: X5365<br />Stepping: B3<br />Number of CPU Cores: 4<br />L2 Cache: 8MB per cpu (2x 4MB)<br />CPUID: 06F7<br />Multipler: 9x<br />Maximum Vcore: 1.4125v<br />PECI Enabled: Yes<br />Enhanced Intel Speedstep Technology: Yes<br />Enhanced Halt State (C1E): Yes<br />Execute Disable Bit (XD): Yes<br />Intel 64 Technology: yes<br />Intel Virtualisation Technology: Yes<br />Packaging: LGA771 (FC-LGA6)<br /><br />The more observant amongst you will have already noted that the vcore is higher than any of other core 2 processors at this point, this in turn has increased the thermal output to around 150w for this particular model. Slower cpus in the series such as the X5355 at 2.66ghz produce around 120w.<br /><br />The question everyone is asking “ok, well how much do they cost?”. That is a rather difficult question to answer as you can only really buy them from the Apple Store in the shape of a Macintosh Pro. Hardly an ideal situation right now for the majority of enthusiasts! The only figures we can give you are for the slower X5355 cpu’s which cost around $1200 each at Newegg. The S5000VXN motherboard is around £350/$500 and the fully buffered memory is around £120/$135 per gigabyte. This certainly isn’t a system you would build to play solitaire on, that’s for sure.<br /><br />Intel’s S5000VXN motherboard gains many aspects from the workstation class heritage, including 2 CPU sockets, eight DIMM slots (max of 32GB), six sata ports with Raid 0/1/10, dual GigE ports and High Definition Audio.<br /><br />This heritage however has a downside, and that is the lack of support right now for multi GPU as the board has only one PCIe x16 slot. We also have a couple of PCIe x4 slots and a pair of PCI-X slots. The board is huge and measures 13 inches by 12 inches and you will need a large extended ATX chassis to house it. I ended up picking up a Rev 2 Thermaltake Armor Black with a 25cm (yes centimeter) case fan which more than accommodated the components while keeping everything running nice and cool.<br /><br />The S5000VXN bios (rather unfortunately) has no options for overclocking so it will not prove popular with those who like to tweak and pry every ounce of performance out of their systems, however after a few weeks of testing we failed to have one BSOD, one hang, failed post or any other glitches, so perhaps there is something to be said for just leaving things alone.<br /><br />Intel also supplied a Coolmaster 850W PSU because the S5000VXN requires both an eight pin auxiliary power connector AND a four pin one, combined. The first mobo we have seen with this in our labs.<br /><br />Again we can see the parentage of the motherboard with the use of full buffered DIMMS (FB-DIMMs). These are firmly routed in server class systems, adding slight latency and power draw while offering better signal integrity (less erroring) and potentially higher bandwidth. These modules draw 5w per module more, when compared with standard DDR2 memory. We are in two minds about this choice, the added integrity is always something we wish for, however the latency and rather exclusive nature of the FB DIMMS proves to be a rather unusual choice by Intel.<br /><br /><br />8GB of sexy Fully Buffered DDR2<br /><br />Crucial were very kind to supply us with FB DIMM’s for our testing at very late notice, and they have proved to be an reliable and great value for money option – they also are supplied with a sexy blue heatspreader which is always a bonus. We have always rated Crucial memory highly on Driver Heaven and I use it in my own home server so I know they will last the distance in such an important system.Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-39908664018134223642007-06-24T08:32:00.000-07:002007-06-24T08:45:37.616-07:00Intel's Core 2 Extreme QX6700 processorIntel's Core 2 Extreme QX6700 processor<br />Quad-core computing arrives on the desktop<br />by Scott Wasson — November 2, 2006<br /><strong>แจก Cursor Onion </strong></span><br><br><br><a href="http://www.uploadtoday.com/download/?04ac8aa39e4a3d8ca111e18f49f0b6f9">http://www.uploadtoday.com/download/?04 … 8f49f0b6f9</a><br><br><img class="postimg" src="http://img238.imageshack.us/img238/1888/onionhi0hd8.gif" alt="http://img238.imageshack.us/img238/1888/onionhi0hd8.gif"><br /><br />YOU'VE GOTTA LIKE Intel's Core 2 Duo processors. After struggling mightily with performance and power consumption problems in the latter-day Pentiums, Intel came roaring back with the Core 2 Duo, producing a chip that goes like stink without spinning the electric meter into a frenzy. Since it offers a better combination of processing power, energy efficiency, and overclocking headroom than the Athlon 64, the Core 2 Duo has quickly become an enthusiast favorite, capturing prominent spots in our system guide recommendations and prompting a new round of upgrades for many folks.<br /><br />Now comes the CPU de grâce, a processor that takes advantage of the Core 2 Duo's modest heat output by cramming two of those chips together into a single socket, a product Intel can plausibly claim is the world's first quad-core CPU. The Core 2 Extreme QX6700 isn't exactly cheap and doesn't run especially cool, but it will turn your spare bedroom into the computing equivalent of a government astrophysics lab and make the neighbors terribly jealous—provided your neighbors are total geeks.<br /><br />What hath Intel wrought with this quad-core beast? Do four CPU cores make sense in a desktop PC, and what sort of applications can really take advantage of such power? Let's have a look.<br /><br />Core 2 Duo times two equals Kentsfield<br />We won't dwell too long on the specifics of the Core 2 Extreme QX6700. This product, which lived its early life going by the code-name Kentsfield, really is two Core 2 Duo chips mounted together on the same package. If you want to know more about the Core 2 Duo's basic technology, I suggest you read our review of that processor. Intel has used this multi-chip packaging technique in the past to create "dual-core" processors, such as the "Presler" Pentium D. Lashing together two separate chips rather than making one large chip makes good sense from an economic standpoint, because smaller die areas tend to make for higher yields of good chips from each wafer.<br /><br />The result of this multi-chip fusion is a processor that plugs into a regular LGA775-style socket and packs four processing cores alongside a total of 8MB of L2 cache. Cosmetically, it looks for all the world like any other recent Intel desktop CPU.<br /><br /><br />The Core 2 Extreme QX6700<br /><br />But here's a fancy illustration Intel came up with to show what's under the hood:<br /><br />The Core 2 Extreme QX6700 runs at 2.66GHz on a 1066MHz front-side bus, so its clock speed matches that of the second fastest Core 2 Duo, the E6700. (The Core 2 Extreme X6800 is the fastest at 2.93GHz.) Intel probably chose not to push any harder on clock speed in order to keep the QX6700 inside of a reasonable power envelope. The E6700's thermal rating, or TDP, is 65W, while the X6800's is 75W. Fittingly, the QX6700's TDP is exactly twice that of the E6700 at 130W. That's quite enough heat production for a desktop processor, and Intel has already established a 130W thermal envelope for Pentium Extreme Edition CPUs that use this same LGA775 infrastructure.<br /><br />In fact, the QX6700 should be compatible with many existing Core 2-compatible motherboards via nothing more than a BIOS update. Some mobo makers have already published compatibility lists for Kentsfield. Then again, Intel says previous revisions of its own D975XBX "BadAxe" mobo aren't designed for use with the QX6700, so nothing is certain. You'll want to check with the motherboard maker to ensure compatibility before taking the plunge.<br /><br />Because the QX6700 is an Extreme Edition processor, it comes with a customarily robust price tag of $999 and an unlocked upper multiplier to facilitate easy overclocking. Intel also plans to introduce a less expensive Core 2 Quad Q6600 CPU at some point in the first quarter of next year. That product will run at 2.4GHz and have a TDP rating of 105W.<br /><br />Quad-core's performance challenges<br />The Core 2 Extreme QX6700 may be the apex of awesomeness in processors today, but it does face some formidable performance challenges, both due to its own nature and because of external factors. As a multi-chip package, the QX6700 contains two copies of a relatively well-integrated dual-core design. The two cores on each chip share a 4MB L2 cache between them, complete with dynamic partitioning and the ability to hand off ownership of data from one core to the next. Unfortunately, the integration between the QX6700's two chips is less than ideal.<br /><br />Although they occupy the same package, their only means of communication is the system's front-side bus. The two chips must coordinate to ensure the sanity of the contents of their respective L2 caches via this bus. That will sometimes mean writing modified data out of one chip's cache into main memory and then reading it back into the other chip's cache—a positively eternal operation in CPU time. Both chips use this same bus to talk with the rest of the system, including main memory and I/O devices. Also, the presence of three electrical loads on the bus—two CPU chips and the core-logic chipset's north bridge—complicates matters. Someone looking to overclock his system's FSB may find less success with a Core 2 Quad or QX6700 than with a standard-issue Core 2 Duo.<br /><br />If all of that sounds complex, just wait until you dig into the software issues. In order to take advantage of multi-core processors, software applications must execute by means of multiple threads. Today, very few games and not many other applications are multithreaded. We do try to take advantage of multithreaded applications when possible in our CPU test suite, but that's more difficult to do for four cores than for two. Many of the early optimizations for multi-core processors only use two threads, so their performance benefits are fully realized on a dual-core CPU.<br /><br />There are reasons for this situation. For instance, one of our test apps, the MP3 encoding program LAME MT, employs a technique called linear pipelining that processes a portion of its work one frame ahead of the main thread and then buffers the result for later use. This method uses only two threads and can't take advantage of more than two CPU cores, but it is relatively easy to program. LAME MT's author says of linear pipelining: "In general, this approach is highly recommended, for it is exponentially harder to debug a parallel application than a linear one." On a similar note, we have seen measurable performance gains in dual-core systems using graphics drivers that offload some vertex processing to a second thread, but Nvidia's drivers, at least, don't appear to benefit from the presence of more than two cores.<br /><br />The thread scheduling mechanism in Windows presents another challenge for quad-core processors, because it doesn't always make the best decisions. During our testing, for example, we found that the Core 2 Extreme QX6700 was turning in substantially lower performance running the same single-threaded task—a POV-Ray scene render—than the like-clocked Core 2 Duo E6700. This behavior was consistent across multiple benchmark runs and a little bit puzzling, until we looked at the Windows Task Manager as this process ran. Turns out the rendering work was bouncing around across all four of the QX6700's cores, playing havoc with cache locality and the like.<br /><br />For the most part, you can expect the Core 2 Extreme QX6700 to perform like a Core 2 Duo E6700 in applications that use only one or two threads, but the QX6700 may prove slower in some cases due to additional bus overhead or bad thread management in Windows. Of course, when applications use more than two threads or more than two apps are running at once, the QX6700 will pull the tab back and pop open a can of whupass. We have some applications like that in our test suite, so you can see quad-core's true potential.<br /><br />That potential, by the way, will almost certainly be more fully realized by future applications, especially games. Software developers know that multi-core processors are the future, and high-profile game development houses have been working on game engines that use multiple threads to handle various tasks. Heck, they practically have to given that the Xbox 360 and the PlayStation 3 have multi-core CPUs. Doing this kind of thing well is by no means a trivial undertaking, but the general trajectory seems to involve spinning off threads for specific game elements like A.I., physics, rendering, and audio. Industry giants like Microsoft and Intel have been pouring resources into helping the conversion to multithreading happen, and I'm convinced that it will.<br /><br />If you're not convinced, perhaps a couple of statements that Intel forwarded to us from key game developers will help. Here's Tim Sweeney, Founder and President of Epic Games:<br /><br /> Multi-core computing is the new standard for PC games, and we at Epic are thrilled to see Intel leading the industry forward with Core 2 Extreme. Its four high-performance CPU cores enable a new level of realism in games, with realistic physics simulation, character animation, and other computationally-intensive systems. <br /><br />And here's Gabe Newell, President and co-founder of Valve:<br /><br /> Quad-core will change every aspect of PC gaming. It will change how we create our games, how we provision our service, and how we design our games. The scalability we've seen in graphics over the last few years will now extend to physics, AI, animation, and all the systems which are critical to moving beyond the era of pretty but dumb games. <br /><br />I don't think these guys are just issuing blanket statements of support in order to play nice. That's not been their style, historically. In fact, we will have more coverage of the specifics of Valve's multithreading efforts very soon, so stay tuned for that.<br /><br />Between now and when those next-generation game engines arrive, owners of quad-core processors will have to find other ways to take full advantage of their CPUs. The test results on the following pages offer numerous examples of applications that use four threads, and beyond that, there's always the prospect of really, really good multitasking. My initial reaction is that you don't need four cores for good multitasking. Despite frequent abuse, my current Athlon 64 X2-based desktop system rarely slows down, and when it does, available CPU time isn't the likely culprit. Then again, I sure wouldn't complain about having four cores at my beck and call.Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-7169768501563808107.post-50677013366771216622007-06-09T03:52:00.001-07:002008-11-06T18:46:37.754-08:00AMD goes quad-core with Phenom<a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiH7dGP48bxRUGcULr7XOgUT_tft-cBNt8SJjb9ZE0_U17nMb1thRhYQYuKZRI9NS48VY_LrcJHDd2o35aNoNNB1RYE6VWCSc1NLkC7V5e27CZx9X8Ot-S7Z5ixbmQ3eH4wC64PvsSPG7_4/s1600-h/AMD-Phenom_550x413.jpg"><img style="display:block; margin:0px auto 10px; text-align:center;cursor:pointer; cursor:hand;" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiH7dGP48bxRUGcULr7XOgUT_tft-cBNt8SJjb9ZE0_U17nMb1thRhYQYuKZRI9NS48VY_LrcJHDd2o35aNoNNB1RYE6VWCSc1NLkC7V5e27CZx9X8Ot-S7Z5ixbmQ3eH4wC64PvsSPG7_4/s320/AMD-Phenom_550x413.jpg" border="0" alt=""id="BLOGGER_PHOTO_ID_5074016108116143378" /></a><br /> THEME WINDOWS VISTA<br /><br /><a href="http://www.uploadtoday.com/download.php?748ef15f70baac54807177b692abc52d">Download THEME WINDOWS VISTA </a><br /><br /><br /><a href="http://sv1.gushare.com/file.php?file=62710732931b72ea2d72c8f725462e68">Theme Vista Xp</a><br /><br /><br />AMD goes quad-core with Phenom<br /><br />Advanced Micro Devices says its badly needed quad-core desktop processors are on the way, and they'll arrive bearing a new name.<br /><br />Later this year, AMD will unveil its Phenom processors in quad-core and dual-core iterations. Two quad-core chips will be available in the second half of the year, the Phenom FX and the Phenom X4, and a dual-core chip based on a similar design called the Phenom X2 will also appear by the end of the year.<br /><br />The Phenom brand will become the moniker for AMD's performance chips going forward, said Leslie Sobon, director of the company's desktop division. The Athlon 64 X2 brand will remain for mainstream chips and Sempron will continue to bring up the rear, she said.<br />Photo: Powered by AMD's Phenom<br /><br />AMD is banking on its design philosophy behind the Phenom chips and their server counterparts, code-named Barcelona, as a way of making up for Intel's lead in the quad-core processor generation. Intel has been shipping quad-core chips for servers and high-end desktops since last year. Those chips are known as "multichip modules" because they are essentially two of Intel's dual-core chips welded together in a package.<br /><br />But AMD chose to build a single chip with four cores, which the company believes will result in better performance because information will not have to leave one core to visit its neighbor. It's the same debate over an integrated memory controller and point-to-point links that propelled AMD's Opteron and Athlon 64 chips to prominence: Cores that are directly linked offer better performance than cores that have to exchange information by leaving the chip.<br /><br />Intel contends that by improving the speed and performance of its cache memory and the front-side bus--that off-chip bridge between cores--it can offer excellent performance and sidestep manufacturing concerns. Because AMD has yet to deliver its quad-core chips, the debate is mostly aesthetic, but it could become an important distinction if Barcelona and the Phenom chips open a significant performance advantage over Intel's currently shipping quad-core processors later this year.<br /><br />Of course, Intel isn't standing still. It will deliver new quad-core chips later this year, and in 2008, it will introduce chips that incorporate the same integrated memory controller and point-to-point links as AMD's with its Nehalem generation of chips.<br />Now on News.com<br />It's not TV--or HBO. It's the Internet Photos: The greatest arcade games of the '80s Week in review: Cell phone hang-up Extra: A dogged Web mag pioneer<br /><br />But AMD is desperate for the Phenom and Barcelona processors to arrive so it can stabilize its average selling prices. The company has been suffering from Intel's lead in the quad-core race, since it has had to aggressively discount its dual-core processors to compete with Intel's offerings, especially in the server arena.<br /><br />Barcelona will come first, scheduled for a "mid-2007" introduction with systems becoming available over the remainder of the year and into next year. The Phenom processors are scheduled for the second half of the year.<br /><br />Around the time of the Phenom launch, AMD will expand upon its "4x4" idea from last year with a product code-named FASN8. (The company swears that's not the real name.) FASN8 is designed for the most performance-hungry PC builders out there, with the ability to hold two quad-core Phenom processors, AMD's new ATI Radeon HD 2900 XT graphics chip, and a new chipset. Intel plans to release a similar product for its quad-core chips.Unknownnoreply@blogger.com1tag:blogger.com,1999:blog-7169768501563808107.post-59362046610606802362007-06-09T03:50:00.000-07:002007-06-09T03:51:07.228-07:00Intel: Quad core to turbocharge chipsSAN FRANCISCO--PC performance will increase 70 percent for some applications with Intel's new "Kentsfield" quad-core processor coming in November, company executives said Tuesday.<br /><br />The performance jump compares the 130-watt, 2.66GHz Kentsfield, to be called the Core 2 Extreme QX6700, with the current speed champ, the 80-watt, 2.93GHz dual-core Core 2 Extreme X6800, said Steve Smith, director of group operations in Intel's Digital Enterprise Group, in a briefing here at the Intel Developer Forum.<br /><br />In addition, the quad-core "Clovertown" processor for servers, to be called the Xeon 5300 and also scheduled to arrive in November, will be about 50 percent faster than the current "Woodcrest" Xeon 5100 at the same 80-watt power level, Smith said. The performance improvement was measured with a test of integer-processing speed.<br /><br />Intel is eager to tout its quad-core models, which are arriving months earlier than comparable products from rival Advanced Micro Devices. That's a change from 2005, when the companies were neck-in-neck delivering dual-core chips, but Intel representatives insisted "it's not a race."<br /><br />The companies are employing very different strategies in their move to quad-core. AMD's models, due to arrive in mid-2007, will have four processing cores on a single slice of silicon.<br /><br />In comparison, Intel combines two dual-core chips in a single package that plugs into a single chip socket. Kentsfield uses two Conroe chips, and Clovertown uses two Woodcrest chips, for example.<br /><br />"The advantage we have by the approach we have is being first," Smith said. "We expect to ship very large volumes of quad-core in servers before we expect our competitors to ship any."<br /><br />Smith argued that there are advantages besides time-to-market with Intel's multichip package approach. For one thing, the company can use the same chips for either dual-core or quad-core products, making it easier to match its product mix to market demands. And its yields--the fraction of usable chips that can be carved from each silicon wafer--are higher.<br /><br />"We have over a 20 percent increase in good quad cores per wafer by picking the two-die multichip package approach," Smith said. "That translates into cost savings for Intel of at least 10 percent in manufacturing cost."<br /><br />AMD sees things differently. Intel's approach means heating problems, computer communication bottlenecks and overly complex product road maps, said John Fruehe, worldwide business development manager for Opteron, the company's rival to Intel's Xeon line.<br /><br />When it comes to electrical power, for example, Woodcrest chips that consume 65 watts turn into 80-watt Clovertown models, and 80-watt Woodcrests become 120-watt Clovertowns. Intel may prefer to compare the two 80-watt models, but customers see things differently, he said: "Most customers buying in the high bin today are going to continue to go with the high bin."<br /><br />Intel plans future quad-core models that consume less power. In the first quarter of 2007, Intel will release mainstream Kentsfield chips, called Core 2 Quad, that consume 105 watts. And in "early 2007" will come 50-watt Clovertowns, Smith added.<br /><br />In addition, Intel will release a quad-core chip for single-processor servers in the first half of 2007, Smith said.<br /><br />Intel's manufacturing technology today can produce circuitry elements measuring 65 nanometers, but the company in 2007 will move to a 45-nanometer process that will mean more electronics on a single chip. Intel will sell quad-core chips built with the 45-nanometer process using both the multichip and monolithic single-chip approach, Smith said in an interview.<br />Now on News.com<br />It's not TV--or HBO. It's the Internet Photos: The greatest arcade games of the '80s Week in review: Cell phone hang-up Extra: A dogged Web mag pioneer<br /><br />Adding new processor cores may sound like an easy way to boost PC performance, but software must be able to take advantage of it for customers to actually benefit. Server software often already works well on multicore and multiprocessor computers, with programs already "multithreaded" to run in independent pieces, but Intel is working on coaxing programmers of desktop software to follow suit.<br /><br />"The application base motivates people to either value (quad-core chips) or not. If you're doing media or content creation, it's a fantastic product, and we'll see very rapid adoption. But if you look at mainstream business PCs, it may be some time before you see the benefits there," Smith said.<br /><br />It's an important issue: Software that isn't multithreaded can sometimes run more slowly on chips with more cores. To avoid problems from higher power consumption, quad-core chips typically run at a clock speed about 10 percent slower than their dual-core brethren, Smith said.<br /><br />Intel's Extreme chip products are aimed at hard-core gamers who want every smidgen of performance, and game producers are working to adapt their software. One such company is Remedy, which demonstrated a game called "Alan Wake" at the Intel show.<br /><br />The game is designed to farm tasks to different processor cores, said Markus Maki, director of development, in an interview. There are three major program threads and each can occupy a core of its own: one for the main game action, one for simulating physics of game objects and one for preparing terrain information that's later sent to the graphics chip for rendering. A fourth core can handle other threads, including playing sound and retrieving data from a DVD, Maki said.Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-41450324872804875612007-06-09T03:41:00.000-07:002007-06-09T03:42:08.255-07:00AMD quad-core Barcelona laid bareMPF 2006 No part untouched<br /><br />By Charlie Demerjian: พุธ 11 ตุลาคม 2549, 17:22<br />AMD LAID OUT a bit more about Barcelona today at MPF, focusing in on six areas. They talked about SSE128, enhanced IPC, efficient memory use, better caches, virtualization and power management.<br /><br />In the macro sense of things, Intel is chasing AMD, but on the micro level, the opposite is true. The talk was given by Ben Sander of AMD, you can read it on his nametag if you don't believe me.<br /><br />[Ben Sander of AMD]<br /><br />Barcelona is the first native quad-core AMD CPU, commonly but wrongly referred to as K8L. It is the first real new core from the chipmaker in quite a while, not merely a massaged version of what came before. You should be seeing it in Q2/07, although some whispers are now saying Q3.<br /><br />Other than four cores, the most obvious difference is the new widened SSE instructions. On the pre-Barcelona parts, SSE was done in 64 bit chunks, so if you wanted to do a 128b operation, you needed two passes, possibly more. With the widening of SSE, it should immediately double throughput on SSE instructions. Obviously media operations will benefit, but HPC and FP heavy ops will get a solid kick in the pants too.<br /><br />In addition to the obvious width change, several less noticeable changes were made to support it. Instruction fetch was upped from 16B/cycle to 32B and support for unaligned load ops was added and cache bandwidth was doubled to support this. Last but not least the FP scheduler was widened from 64 to 128b.<br /><br />The enhanced IPC is more a case of little improvements adding up to a bigger bang rather than any single thing standing out. The SSE improvements add a bit here and there to start with, and a better branch predictor adds to this. It is bigger and better with a larger history, a dedicated 512 entry indirect predictor, and the return stack is doubled in size.<br /><br />In the catching up with Intel side of things, added a sideband stack optimizer, out of order load execution and data dependent divide latency. They also upped the TLB to support 1G pages, 48-bit physical addressing, and improved the ITLB and DTLBs. There are also more fastpath instructions and a few more bit manipulation instructions and SSE extensions.<br /><br />For RAM efficiency, one of the main things they did was make the two memory controllers on the chip act independently, up to Rev G they could only act in lockstep. This lets AMD hit two memory locations at once, potentially a big win for server type apps, but for single users, it's benefit is less clear.<br /><br />On top of this, they changed the northbridge a lot increasing buffers and adding support for new DRAM types. The Barcelona controller will do FBD if necessary, but the chances of you seeing that are something less than zero. AMD also updated the way paging is done and modified the way write bursting happens.<br /><br />Additionally, one of the big complaints I hear is prefetch, and that has been comprehensively addressed. They now track positive, negative and non-unit strides, and have a dedicated prefetch buffer. On top of that, Barcelona is much more aggressive in how they fill idle ram cycle and updated the core prefetchers on both the L1D and L1I side.<br /><br />The newer L3 cache is called a 'victim cache', it sits on top of the existing discrete L2 caches, and is shared among the cores. The big thing here is that if the caches are empty, the request goes to L1 cache. If that fills, the data line is evicted to L2, and when L2 fills, it goes to L3. If a core reads from L3, there are one of two things that can happen. If it is data, the line is moved to L1D, but if it is instructions, the line may be moved to L1I, or it may be copied to L1I and left in L3. The L3 is not exclusive, and the point of this is that code is often shared among the cores while data is far less often. The cache lines have performance hints associated with them that will clue to cores in on the whole copy vs move debate.<br /><br />That brings us to virtualization, a topic we have covered a lot in our Pacifica articles (1, 2, 3 and 4 )The main advance Barcelona brings is that it turns on Nested Page Table support and a few other things that did not make the cut on the Rev F parts. It is also said to reduce world switch time going to the hypervisor and back by 25%.<br /><br />One of the last things they did was to break the CPU and northbridge into separate power planes. This will allow the CPUs to be clocked up and down, and volted up and down independently of the Northbridge. This was a major sticking point in the ramp of the previous iterations of the chip, and I expect big dividends here, and it also saves a lot of power. I am also told that they can change the voltage on cores independently, but that is more of a motherboard issue. Since it is not really supported anywhere on the current platforms, don't look for a BIOS option to turn it on, but if it came back in later platform revisions, I would not be overly surprised.<br /><br />What you have for Barcelona is a CPU that looks a lot like the older revs at the block diagram level, but no part of it is untouched. Some pieces a massively updated, others far less so. In any case, it will add up to significant gains overall, but will it be enough to dethrone Woodcrest 2 core? Stay tuned in the middle of next year for the answer to that.Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-20430617348021900932007-06-09T03:28:00.001-07:002007-06-09T03:28:35.027-07:00Intel Core 2 Extreme QX6700 CPU Quad Core<font size="3">Introduction</font></p><p align="justify"><a href="http://www.intel.com/" target="_blank">Intel</a>, leap ahead. At Intel, they constantly push the boundaries of innovation in order to make people's lives more exciting, more fulfilling, and easier to manage. Their unwavering commitment to moving technology forward has transformed the world by leaps and bounds. They're a company that's always in motion, fueling an industry that never rests. They inspire their partners to develop innovative products and services, rally the industry to support new products, and drive industry standards. Intel does this so that it can collectively deliver better solutions with greater benefits more quickly.</p><p align="justify">Leap ahead, these two words drive focus at Intel. Their job is to find and drive the next leap ahead around technology, education, culture, social responsibility, manufacturing, and more to continuously encourage their customers, partners, consumers, and businesses to join them as they continue to take exciting leaps forward. In the end, it's not just about making technology faster, smarter, and cheaper. It's about using that technology to make life better, richer, and more convenient for everyone it touches. Intel has a history of leading bold and positive change. Intel's passion for technology has transformed the world.</p><p align="center"><a href="/images/reviews/qx6700/cpu-qx6700-bg-02.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-mm-02.jpg" border="0" height="315" width="420"></a></p><p align="justify">After the incredible launch of Intel's Conroe series it's not too easy to follow that up. But make no mistake as at the end of last year, Intel has launched the world's first quad core desktop processor. The Intel Core 2 Extreme QX6700 is based on the new Kentsfield core. In fact the Kentsfield is nothing more than two Conroe's placed on a single package. Much like Presler before it, Kentsfield is technically a qual core processor with two separate die on the same package. While it is perhaps not as elegant as a true quad core processor, Intel's new quad core processor unquestionably gets the job done.</p><p align="left"><strong><font size="3">Features</font></strong></p><ul><li>Quad Core Processing</li><li>Intel Wide Dynamic Execution</li><li>Intel Smart Memory Access</li><li>Intel Advanced Smart Cache</li><li>Intel Advanced <a id="KonaLink0" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="border-bottom: 1px solid blue; color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static; padding-bottom: 1px; background-color: transparent;">Digital </span><span class="kLink" style="border-bottom: 1px solid blue; color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static; padding-bottom: 1px; background-color: transparent;">Media</span></font></a> Boost</li><li>Intel Virtualization Technology (VT)</li><li>Intel 64 Architecture</li><li>Execute Disable Bit</li></ul><p align="justify">An Intel quad core processor consists of four complete execution cores in one physical processor, all running at the same frequency. All cores share the same packaging and the same interface with the other chipsets and memory. Imagine that a quad core processor is like an eight lane highway, it can handle up to twice as many cars as its four lane predecessor without making each car drive twice as fast. Similarly, with an Intel quad core based PC, people can perform multiple tasks such as <a id="KonaLink1" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">downloading </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">music</span></font></a> and gaming simultaneously more efficiently. Overall, it offers a way of delivering more capabilities while balancing energy efficient performance.</p><p align="center"><strong>Intel Core 2 Extreme QX6700 CPU Quad Core</strong></p><p align="center"><a href="/images/reviews/qx6700/cpu-qx6700-bg-01.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-mm-01.jpg" border="0" height="315" width="420"></a></p><p align="justify">The Intel QX6700, which lived its early life going by the codename Kentsfield, really is two <a id="KonaLink2" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">Core </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">2 </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">Duo</span></font></a> chips mounted together on the same package. Intel actually used this multi-chip packaging technique in the past to create their first <a id="KonaLink3" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">dual </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">core </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">processors</span></font></a>, such as the Pentium D (Presler). Combining two separate chips rather than making one large chip makes good sense from an economic standpoint, because smaller die areas tend to make higher yields of good chips from each wafer. The end result of such multi-chip fusion is a processor that plugs into a regular LGA775 socket and packs four processing cores alongside a total of 8MB of <a id="KonaLink4" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">L2 </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">cache</span></font></a>. And it looks like any other recent Intel desktop CPU.</p><p align="center"><a href="/images/reviews/qx6700/cpu-qx6700-bg-04.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-sm-04.jpg" border="0" height="150" width="200"></a> <a href="/images/reviews/qx6700/cpu-qx6700-bg-05.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-sm-05.jpg" border="0" height="150" width="200"></a></p><p align="justify">The Core 2 Extreme QX6700 is clocked at the same frequency as the Core 2 Duo E6700, namely 2.67GHz with a 1066MHz front side bus. So its clock speed matches that of the second fastest Core 2 Duo, the E6700. Yes indeed, the current fastest Intel <a id="KonaLink5" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">dual </span><span class="kLink" style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;">core</span></font></a> CPU is still the Core 2 Extreme X6800 set at 2.93GHz. Initially, there will only be the one quad core processor in Intel's line up, but a second will follow this year. When the Core 2 Quad Q6600 is announced, it will not come as much of a surprise to you to find that it will be clocked at the same speed as the Core 2 Duo E6600.</p><p align="center"><a href="/images/reviews/qx6700/cpu-qx6700-bg-06.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-sm-06.jpg" border="0" height="150" width="200"></a> <a href="/images/reviews/qx6700/cpu-qx6700-bg-07.jpg" target="_blank"><img alt="Copyright 2007 - MVKTech" src="/images/reviews/qx6700/cpu-qx6700-sm-07.jpg" border="0" height="150" width="200"></a></p><p align="justify">The Intel Core 2 Extreme qual core processor is the ideal desktop processor for those who want an outstanding multimedia and gaming experience. Designed for gamers and PC enthusiasts who perform multiple complex tasks simultaneously, the Intel Core 2 Extreme QX6700 provides exceptional performance for highly threaded digital media creation software and ultra realistic games. For experienced enthusiasts the Core 2 Extreme QX6700 bus ration locks have been removed. This offers added technical flexibility in tuning your <a id="KonaLink6" target="_top" class="kLink" style="text-decoration: underline ! important; position: static;" href="#"><font style="color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static;" color="blue"><span class="kLink" style="border-bottom: 1px solid blue; color: blue ! important; font-family: Arial,Helvetica,sans-serif; font-weight: 400; font-size: 10px; position: static; padding-bottom: 1px; background-color: transparent;">system</span></font></a>, even beyond the specified limits.</p><p align="left"> </p>Unknownnoreply@blogger.com0tag:blogger.com,1999:blog-7169768501563808107.post-84061158001170641922007-06-09T03:26:00.001-07:002007-06-09T03:26:05.042-07:00Intel® Core™ 2 Extreme Quad-Core Processor QX6700<img src="header.jpg" border="0" height="367" width="550"></td><br /> </tr><br /> </tbody></td><br /> </tr><br /> </tbody><br /> <p align="left"><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> สวัสดีเพื่อนสมาชิกโอเวอร์คล๊อกโซนทุท่านครับ วันนี้ผม <font face="Verdana, Arial, Helvetica, sans-serif"><em>spin <br /> 9</em></font> กลับมาทักทายทุกท่านอีกครั้งกับเรื่องราวที่น่าสนใจครั้งใหญ่ส่งท้ายปลายปี <br /> นั่นก็คือวันนี้ หรือ วันที่ 2 พฤศจิกายน 2549 ถือเป็นฤกษ์งามยามดีในการเปิดตัวซีพียู <br /> "ควอด-คอร์" ตัวแรกของแพลทฟอร์มเดสก์ท็อปจากยักษ์ใหญ่อย่างอินเทล <br /> หรือถ้าจะพูดให้ฟังดูน่าตื่นเต้นกว่านั้นก็คือ วันนี้เราจะได้เห็นซีพียูที่มีแกนประมวลผลมากถึง <br /> 4 แกน อันจะเป็นจุดเริ่มต้นของเทคโนโลยี มัลติ-คอร์ ในอนาคตนั่นเองครับ</font></p><br /><br /> <p align="left"><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> ย้อนกลับไปเมื่อกลางปีที่แล้วนี้เอง (กลางปี 2548) ผ่านไปเพียงราวๆ <br /> หนึ่งปีเศษๆ กับจุดเริ่มต้นครั้งแรกสุดของซีพียู ดูอัล-คอร์ <br /> (Dual-Core Processor) ที่อินเทลได้ทำการเปิดตัวซีพียูดูอัล-คอร์ตัวแรกในชื่อของ <br /> <a href="../pd_820/index.html" target="_blank"><u>Intel <br /> Pentium D Processor</u></a> พัฒนาเรื่อยมาถึงยุคของ <a href="../c2e_x6800/index.html" target="_blank"><u>Intel <br /> Core 2 Duo Processor</u></a> ซึ่งก็ยังคงเป็นดูอัล-คอร์อยู่ <br /> (มีแกนประมวลผล 2 แกนในซีพียูตัวเดียว) และได้กลายเป็นมาตรฐานของซีพียูในปัจจุบันไปเป็นที่เรียบร้อย <br /> ชนิดที่ว่าใครจะหาซื้อเครื่องคอมพิวเตอร์เดสก์ท็อปซักเครื่องในปัจจุบัน <br /> ก็ต้องมองหาซีพียูที่เป็นดูอัล-คอร์เอาไว้ก่อน เพราะเทคโนโลยีดูอัล-คอร์นั้น <br /> ช่วยให้การประมวลผลและการใช้งานจริงของเครื่องคอมพิวเตอร์ในปัจจุบัน <br /> มีประสิทธิภาพที่เพิ่มมากขึ้นอย่างเห็นได้ชัด.. ชัดกว่าการเพิ่มความเร็วสัญญาณนาฬิกาหรือคล๊อกสปีด <br /> ที่ในอดีตซีพียูได้แข่งขันกันทำคล๊อกสปีดให้สูงขึ้นเรื่อยๆ <br /> จนเริ่มมาถึงทางตัน </font></p><br /> <p align="left"><font color="#ffcc00" face="Geneva, Arial, Helvetica, sans-serif" size="1"><strong> <br /> <font color="#ffffff" face="Verdana, Arial, Helvetica, sans-serif">How <br /> can Intel achieve 10X performance over time?</font></strong></font></p><br /> <table align="center" border="1" bordercolor="#333333" cellpadding="0" cellspacing="0" width="89%"><br /> <tbody><tr> <br /> <td height="238"> <div align="center"><a href="cpu_trend.jpg" target="_blank"><img src="cpu_trend_resize.jpg" border="0" height="289" width="550"></a></div></td><br /><br /> </tr><br /> </tbody></table><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> จากการคาดการณ์ของอินเทล โดยใช้ซีพียู Intel Pentium 4 Processor <br /> ในปี 2000 เป็นตัวยืนพื้นนั้น อินเทลได้คาดการณ์ว่า หากไม่มีการพัฒนาทางด้านมัลติ-คอร์ <br /> (การใช้แกนประมวลผลมากกว่าหนึ่งแกนในซีพียูตัวเดียว) อินเทลจะสามารถเพิ่มประสิทธิภาพของซีพียูได้เพียง <br /> 3 เท่าตัว ในระยะเวลา 8 ปี (คาดการณ์ถึงปี 2008) แต่ถ้าอินเทลต้องการจะเพิ่มประสิทธิภาพในการทำงานของซีพียูมากถึง <br /> 10 เท่าตัวนั้น วิธีเดียวที่จะทำได้ก็คือ การใช้เทคโนโลยี <br /> ดูอัล-คอร์ หรือ มัลติ-คอร์เข้ามาช่วยนั่นเอง นี่จึงเป็นเหตุผลหลักที่อินเทลหันมาทุ่มเทพัฒนาซีพียูในระดับมัลติ-คอร์มากขึ้น <br /> โดยค่อยๆ ลดความสำคัญของซีพียูในระดับซิงเกิล-คอร์ลงครับ <br /> <em>(ข้อมูลจากงาน Intel Developer Forum, Taiwan Fall 2006)</em></font></p><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> และวันนี้ 2 พฤศจิกายน 2549 ... จุดกำเนิดแห่งเทคโนโลยีมัลติ-คอร์อย่างแท้จริงก็ได้ถือกำเนิดขึ้น <br /> กับซีพียูระดับ "ควอด-คอร์" ตัวแรกของแพลทฟอร์มเดสก์ท็อป <br /> ที่มีแกนประมวลผลมากถึง 4 แกนในซีพียูตัวเดียว ภายใต้ชื่อของ <br /> Intel Core 2 Extreme Quad-Core Processor QX6700 ... สุดยอดซีพียูในระดับเอ๊กซ์ตรีมตัวใหม่ของอินเทล <br /> ที่วันนี้เราจะได้มาชมถึงเบื้องลึก พร้อมผลการทดสอบประสิทธิภาพอย่างละเอียดกันครับ</font></p><br /> <p><font color="#ffffff" face="Verdana, Arial, Helvetica, sans-serif" size="1"><strong>Introducing <br /> the First Quad-Core Desktop Processor:<br><br /> <font color="#ffcc00">Intel Core 2 Extreme Quad-Core Processor <br /> QX6700</font></strong></font></p><br /><br /> <table align="center" border="1" bordercolor="#333333" cellpadding="0" cellspacing="0" width="89%"><br /> <tbody><tr> <br /> <td height="238"> <div align="center"><img src="C2EQX_resize.jpg" border="0" height="550" width="550"></div></td><br /> </tr><br /> </tbody></table><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> อินเทล คอร์ 2 เอ๊กซ์ตรีม ควอด-คอร์ โปรเซสเซอร์ QX6700 <br /> ถือเป็นซีพียูเดสก์ท็อปรุ่นแรกของโลกที่มีแกนประมวลผล 4 <br /> แกนอยู่ในซีพียูตัวเดียวครับ ซึ่งก่อนที่จะไปดูถึงความแตกต่างและประสิทธิภาพของมันนั้น <br /> ผมต้องขอทำความเข้าใจถึงสถาปัตยกรรมและที่มาที่ไปของเจ้า <br /> QX6700 ตัวนี้เสียก่อน ว่าอินเทลพัฒนามันขึ้นมาได้อย่างไร <br /> และซีพียูระดับควอด-คอร์จะเข้ามาอยู่ที่ตำแหน่งไหนในตลาดเดสก์ท็อปปัจจุบัน</font></p><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> อินเทล คอร์ 2 เอ๊กซ์ตรีม ควอด-คอร์ โปรเซสเซอร์ QX6700 <br /> มาในรหัสพัฒนา Kentsfield ซึ่งเป็นซีพียูที่มีพื้นฐานจากสถาปัตยกรรม <br /> Core Microarchitecture ของอินเทลอยู่เหมือนกับซีพียูอินเทล <br /> คอร์ 2 ดูโอ หรือรหัสพัฒนา Conroe ในปัจจุบันครับ ซึ่งแน่นอนว่า <br /> มันจะยังคงมีฟีเจอร์ต่างๆ ที่อินเทล คอร์ 2 ดูโอ มีอย่างครบถ้วน <br /> และเบื้องลึกที่น่ารู้ก็คือ เจ้า Kentsfield หรือซีพียูควอด-คอร์ตัวแรกจากอินเทลนี้ <br /> แท้จริงแล้ว ทางอินเทลได้นำเอาชิป Dual-Core จำนวนสองตัวเข้ามารวมกันไว้ภายใต้ซีพียูแพ็คเกจเดียวกัน <br /> (ก็คือเอา Conroe สองตัวมาวางไว้คู่กัน เพื่อรวมดูอัล-คอร์สองตัว <br /> ให้กลายเป็น 4 คอร์) และพัฒนาเทคโนโลยีในการติดต่อสื่อสารระหว่างแกนประมวลผลแต่ละแกน <br /> เพื่อให้ระบบมองเห็นเป็น 4 คอร์นั่นเองครับ</font></p><br /><br /> <table align="center" border="0" width="77%"><br /> <tbody><tr> <br /> <td height="189" width="47%"> <div align="center"> <font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> <a href="http://www.overclockzone.com/spin9/review/vga/gigabyte/x800pro-256mb/DSCN0792.JPG" target="_blank"> <br /> </a></font> <br /> <table border="1" bordercolor="#333333" cellpadding="0" cellspacing="0" width="92%"><br /> <tbody><tr> <br /> <td height="185"><font face="MS Sans Serif, Tahoma, sans-serif" size="1"><a href="C2E-Cores.jpg" target="_blank"><img src="C2E-Cores_resize.jpg" border="0" height="209" width="280"></a></font></td><br /> </tr><br /> </tbody></table><br /><br /> </div></td><br /> <td width="53%"><p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> ภายในซีพียู Intel Core 2 Extreme Quad-Core QX6700 <br /> นั้น ถ้าแกะฝา heatspreader ออกแล้ว เราก็จะมองเห็นแกนประมวลผลแยกออกเป็นสองแกนอย่างในภาพครับ <br /> โดยแต่ละแกนประมวลผลที่เห็นนี้ ก็คือแกนประมวลผลที่มาจากคอร์ <br /> Conroe ที่ภายในเป็นดูอัล-คอร์นั่นเอง เมื่อดูอัล-คอร์สองชิปมาอยู่ด้วยกัน <br /> ก็ทำให้ซีพียูตัวนี้มีแกนประมวลผลรวมมากถึง 4 แกน <br /> หรือ ควอด-คอร์</font></p></td><br /> </tr><br /> </tbody></table><br /> <br><br /> <table align="center" border="1" bordercolor="#333333" cellpadding="0" cellspacing="0" width="89%"><br /> <tbody><tr> <br /> <td height="238"> <div align="center"><a href="qx6700_dieshot.jpg" target="_blank"><img src="qx6700_dieshot_resize.jpg" border="0" height="360" width="550"></a></div></td><br /><br /> </tr><br /> </tbody></table><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> ภาย die-shot ของซีพียู Kentsfield นั้น ยิ่งแสดงให้เห็นชัดเจนครับ <br /> ว่ามันคือ Conroe จำนวน 2 ตัวมาวางคู่กัน ซึ่งตามสเป็คของ <br /> Conroe แล้ว มันก็คือดูอัล-คอร์ที่มีแคชระดับสองอยู่ภายในมากถึง <br /> 4MB ดังนั้น เมื่อ Conroe สองตัวถูกนำมาวางคู่กัน ก็จะทำให้ <br /> Kentsfield มีแกนประมวลผลรวมแล้ว 4 แกน (2x Dual-Core) และมีแคชระดับสองรวมมากถึง <br /> 8MB (2x 4MB) นั่นเองครับ</font></p><br /> <table align="center" border="1" bordercolor="#333333" cellpadding="0" cellspacing="0" width="89%"><br /> <tbody><tr> <br /> <td height="415"> <br /><div align="center"><a href="qx6700_dieshot.jpg" target="_blank"><img src="qx6700_975x_resize.jpg" border="0" height="413" width="550"></a></div></td><br /> </tr><br /> </tbody></table><br /><br /> <p><font face="MS Sans Serif, Tahoma, sans-serif" size="1"> <br /> ด้วยเหตุผลของสถาปัตยกรรมต่างๆ ที่กล่าวมา ก็น่าจะทำให้พอทราบกันดีนะครับ <br /> ว่าแท้จริงแล้ว Kentsfield ยังคงเป็นซีพียูที่อยู่ภายใต้สถาปัตยกรรม <br /> Core Microarchitecture อยู่เหมือนเดิม ดังนั้น การรองรับของเมนบอร์ดในชิปเซ็ทต่างๆ <br /> ก็ยังคงเหมือนกับการรองรับซีพียู Conroe หรือ คอร์ 2 ดูโอ <br /> นั่นเอง โดยชิปเซ็ทที่รองรับในเบื้องต้น หลักๆ แล้วก็จะเป็นชิปเซ็ทอินเทลตระกูล <br /> 965 Express และ 975X Express ซึ่งเมนบอร์ดบางรุ่น บางยี่ห้อ <br /> ต้องอาศัย BIOS เวอร์ชันใหม่ มารองรับ เพื่อทำให้ระบบมองเห็นซีพียูครบถ้วนทั้ง <br /> 4 คอร์ และใช้งานมันได้อย่างเต็มประสิทธิภาพครับ</font></p><br /> <p> <br /> และวันนี้ สุดยอดซีพียูควอด-คอร์ตัวแรกของแพลทฟอร์มเดสก์ท็อปอย่าง <br /> Intel Core 2 Extreme Quad-Core Processor QX6700 ก็อยู่ในมือผมเป็นที่เรียบร้อยครับ <br /> ไปพบกับเรื่องราวของมันพร้อมประสิทธิภาพในการใช้งานจริงหลากหลายรูปแบบกันได้เลยUnknownnoreply@blogger.com0